Alex F. A. Furtunato

Instituto Federal do Rio Grande do Norte

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Samuel Xavier‐de‐Souza

Universidade Federal do Rio Grande do Norte

Kyriakos Georgiou

University of Bristol

Kerstin Eder

University of Bristol

Vitor R. G. Silva

University of Mons

Luiz F. Q. Silveira

Universidade Federal do Rio Grande do Norte

Carlos Valderrama

University of Mons

Anderson B. N. da Silva

Universidade Federal do Rio Grande do Norte

Victor Hugo Fonseca Oliveira

Universidade Federal de Lavras

Daniel A. M. Cunha

Universidade Federal do Rio Grande do Norte

Eduardo Almeida Neves

Universidade Estadual de Maringá

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Universidade Federal do Rio Grande do Norte

University of Mons

University of Bristol

Universidade Federal de Pernambuco

Nova Southeastern University

Ministério da Agricultura

Instituto Federal do Rio Grande do Norte

Technical University of Denmark

Ørsted (Denmark)

Universidade Federal Rural do Semi-Árido

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Energy-Optimal Configurations for Single-Node HPC Applications

arXiv (Cornell University) (2018)

Vitor R. G. Silva Alex F. A. Furtunato Kyriakos Georgiou Kerstin Eder Samuel Xavier‐de‐Souza

Energy efficiency is a growing concern for modern computing, especially for HPC due to operational costs and the environmental impact. We propose a methodology to find energy-optimal frequency and number of active cores to run single-node HPC applications using an application-agnostic power model of the architecture and an architecture-aware performance model of the application. We characterize the application performance using Support Vector Regression. The power consumption is estimated by modeling CMOS dynamic and static power without knowledge of the application. The energy-optimal configuration is estimated by minimizing the product of the power model and the performance model's outcomes. Results for four PARSEC applications with five different inputs show that the proposed approach used about 14X less energy when compared to the worst case of the default Linux DVFS governor. For the best case of the DVFS scheme, 23% savings were observed, with an overall average of 6% less energy.

10.48550/arxiv.1805.00998

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Energy-Optimal Configurations for Single-Node HPC Applications

arXiv (Cornell University) (2018)

Vitor R. G. Silva Alex F. A. Furtunato Kyriakos Georgiou Kerstin Eder Samuel Xavier‐de‐Souza

Parsec

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PaScal Viewer: A Tool for the Visualization of Parallel Scalability Trends

Lecture notes in computer science (2019)

Anderson B. N. da Silva Daniel A. M. Cunha Vitor R. G. Silva Alex F. A. Furtunato Samuel Xavier‐de‐Souza

Pascal (unit)

Profiling (computer programming)

Extensibility

10.1007/978-3-030-17872-7_15

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The benefits of low operating voltage devices to the energy efficiency of parallel systems

Samuel Xavier‐de‐Souza Eduardo Almeida Neves Alex F. A. Furtunato Luiz F. Q. Silveira Kyriakos Georgiou

Programmable circuits such as general-purpose processors or FPGAs have their end-user energy efficiency strongly dependent on the program that they execute. Ultimately, it is the programmer's ability to code and, in the case of general purpose processors, the compiler's ability to translate source code into a sequence of native instructions that make the circuit deliver the expected performance to the end user. This way, the benefits of energy-efficient circuits build upon energy-efficient devices could be obfuscated by poorly written software. Clearly, having well-written software running on conventional circuits is no better in terms of energy efficiency than having poorly written software running on energy-efficient circuits. Therefore, to get the most out of the energy-saving capabilities of programmable circuits that support low voltage operating modes, it is necessary to address software issues that might work against the benefits of operating in such modes.

Programmer

10.1109/e3s.2017.8246198

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Application Speedup Characterization

Victor Hugo Fonseca Oliveira Alex F. A. Furtunato Luiz F. Q. Silveira Kyriakos Georgiou Kerstin Eder

To make efficient use of multi-core processors, it is important to understand the performance behavior of parallel applications. Modeling this can enable the use of online approaches to optimize throughput or energy, or even guarantee a minimum QoS. Accurate models would avoid probe different runtime configurations, which causes overhead. Throughout the years, many speedup models were proposed. Most of them based on Amdahl's or Gustafson's laws. However, many of those make considerations such as a fixed parallel fraction, or a parallel fraction that varies linearly with problem size, and inexistent parallelization overhead. Although such models aid in the theoretical understanding, these considerations do not hold in real environments, which makes the modeling unsuitable for accurate characterization of parallel applications. The model proposed estimates the speedup taking into account the variation of its parallel fraction according to problem size, number of cores used and overhead. Using four applications from the PARSEC benchmark suite, the proposed model was able to estimate speedups more accurately than other models in recent literature.

Speedup

Characterization

10.1145/3185768.3185770

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When Parallel Speedups Hit the Memory Wall

IEEE Access (2020)

Alex F. A. Furtunato Kyriakos Georgiou Kerstin Eder Samuel Xavier‐de‐Souza

After Amdahl's trailblazing work, many other authors proposed analytical speedup models but none have considered the limiting effect of the memory wall. These models exploited aspects such as problem-size variation, memory size, communication overhead, and synchronization overhead, but data-access delays are assumed to be constant. Nevertheless, such delays can vary, for example, according to the number of cores used and the ratio between processor and memory frequencies. Given the large number of possible configurations of operating frequency and number of cores that current architectures can offer, suitable speedup models to describe such variations among these configurations are quite desirable for off-line or on-line scheduling decisions. This work proposes new parallel speedup models that account for variations of the average data-access delay to describe the limiting effect of the memory wall on parallel speedups. Analytical results indicate that the proposed modeling can capture the desired behavior while experimental hardware results validate the former. Additionally, we show that when accounting for parameters that reflect the intrinsic characteristics of the applications, such as degree of parallelism and susceptibility to the memory wall, our proposal has significant advantages over machine-learning-based modeling. Moreover, besides being black-box modeling, our experiments show that conventional machine-learning modeling needs about one order of magnitude more measurements to reach the same level of accuracy achieved in our modeling.

Speedup

10.1109/access.2020.2990418

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Energy-Optimal Configurations for Single-Node HPC Applications

Vitor R. G. Silva Alex F. A. Furtunato Kyriakos Georgiou Carlos Valderrama Kerstin Eder

Energy efficiency is a growing concern for modern computing, especially for HPC due to operational costs and the environmental impact, considering that processors have an important role in this energy consumption. In this work, we propose a methodology to find energy-optimal frequency and number of active cores to run single-node HPC applications using an application-agnostic power model of the architecture and an architecture-aware performance model of the application. We characterize the application performance using machine learning, specifically the "Support Vector Regression" algorithm. Besides that, the power consumption is estimated by modeling CMOS dynamic and static power without knowledge of the application. So, The energy-optimal configuration is estimated by minimizing the product these two models outcomes, the power model and the performance model. Then, the final model can be used to find better frequency and number of cores to aim energy efficiency application execution. Results were obtained for four PARSEC applications and, with five different inputs shows that the proposed approach used substantially less energy when compared to the DVFS governor, in best cases and worst cases.

Dynamic demand

10.1109/hpcs48598.2019.9188110

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Citations (8)