Massoud Pedram

University of Southern California

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Co-Authors

Yanzhi Wang

Northeastern University

111

Mehdi Kamal

University of Southern California

110

Ali Afzali‐Kusha

University of Tehran

103

Naehyuck Chang

Korea Advanced Institute of Science and Technology

Shahin Nazarian

University of Southern California

Yanzhi Wang

Huazhong University of Science and Technology

Arash Fayyazi

University of Southern California

Mahdi Nazemi

University of Southern California

Xue Lin

Jiangsu University

Qing Xie

North China Electric Power University

Cooperative Institutions

University of Southern California

195

University of Tehran

Southern California University for Professional Studies

Engineering Systems (United States)

Intel (United States)

Institute of Electrical and Electronics Engineers

Seoul National University

University of California, Berkeley

Ahvaz Jundishapur University of Medical Sciences

Chinese Academy of Sciences

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A Reinforcement Learning-Based Power Management Framework for Green Computing Data Centers

Xue Lin Yanzhi Wang Massoud Pedram

Various power management techniques have been exploited to reduce the energy consumption of data centers. In this work, we propose a reinforcement learning-based power management framework for data centers, which does not rely on any given stationary assumptions of the job arrival and job service processes. By carefully designing the state space, the action space, and the reward of a learning process, the objective of the reinforcement learning agent coincides with our goal of reducing the server pool energy consumption with reasonable average job response time. Real Google cluster data traces are used to verify the effectiveness of the proposed reinforcement learning-based data center power management framework.

Data center

Q-learning

Load management

10.1109/ic2e.2016.33

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Citations (35)

Accurate Modeling of the Delay and Energy Overhead of Dynamic Voltage and Frequency Scaling in Modern Microprocessors

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2013)

Sangyoung Park Jaehyun Park DongHwa Shin Yanzhi Wang Qing Xie

Dynamic voltage and frequency scaling (DVFS) has been studied for well over a decade. Nevertheless, existing DVFS transition overhead models suffer from significant inaccuracies; for example, by incorrectly accounting for the effect of DC-DC converters, frequency synthesizers, voltage, and frequency change policies on energy losses incurred during mode transitions. Incorrect and/or inaccurate DVFS transition overhead models prevent one from determining the precise break-even time and thus forfeit some of the energy saving that is ideally achievable. This paper introduces accurate DVFS transition overhead models for both energy consumption and delay. In particular, we redefine the DVFS transition overhead including the underclocking-related losses in a DVFS-enabled microprocessor, additional inductor IR losses, and power losses due to discontinuous-mode DC-DC conversion. We report the transition overheads for a desktop, a mobile and a low-power representative processor. We also present DVFS transition overhead macromodel for use by high-level DVFS schedulers.

Frequency scaling

Microprocessor

10.1109/tcad.2012.2235126

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Citations (122)

Post-layout circuit speed-up by event elimination

Hirendu Vaishnav Chi-Keung Lee Massoud Pedram

We propose a novel technique for post-layout delay optimization. This technique identifies the Boolean space corresponding to late arriving transitions at the outputs of delay-critical subcircuits within the given circuit. The transitions are eliminated from the outputs by implementing the corresponding logic separately and merging them with the original circuit through some control logic. Experimental results suggest that this technique can speed up circuits even when the circuits have already been optimized for delay to the fullest extent.

Asynchronous circuit

Sequential logic

Combinational logic

10.1109/iccd.1997.628870

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Citations (3)

Reversible logic synthesis by quantum rotation gates

Quantum Information and Computation (2013)

Afshin Abdollahi Mehdi Saeedi Massoud Pedram

A rotation-based synthesis framework for reversible logic is proposed. We develop a canonical representation based on binary decision diagrams and introduce operators to manipulate the developed representation model. Furthermore, a recursive functional bi-decomposition approach is proposed to automatically synthesize a given function. While Boolean reversible logic is particularly addressed, our framework constructs intermediate quantum states that may be in superposition, hence we combine techniques from reversible Boolean logic and quantum computation. {The proposed approach results in quadratic gate count for multiple-control Toffoli gates without ancillae, linear depth for quantum carry-ripple adder, and $O(n\log^2 n)$ size for quantum multiplexer.

Toffoli gate

Reversible computing

Quantum circuit

Quantum Logic

Quantum Fourier transform

10.26421/qic13.9-10-3

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Citations (4)

CGTA

Shahin Nazarian Massoud Pedram Tao Lin E. Tuncer

This paper introduces a new current-based cell timing analyzer, called CGTA, which has a higher performance than existing logic cell timing analysis tools. CGTA relies on a compact lookup table storing the output current gain (sensitivity) of every logic cell as a function of its input voltage and output load. The current gain values are subsequently used by the timing calculator to produce the output current value as a function of the applied input voltage. This current and the output load then uniquely determine the output voltage value. Therefore, CGTA is capable of efficiently and accurately computing the output voltage waveform of a logic cell, which has been subjected to an arbitrary noisy input voltage waveform. Experimental results are presented to assess the quality of CGTA compared to other existing approaches.

10.1145/1118299.1118316

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Cofactor Sharing for Reversible Logic Synthesis

ACM Journal on Emerging Technologies in Computing Systems (2014)

Alireza Shafaei Mehdi Saeedi Massoud Pedram

Improving circuit realization of known quantum algorithms by CAD techniques has benefits for quantum experimentalists. In this article, the problem of synthesizing a given function on a set of ancillea is addressed. The proposed approach benefits from extensive sharing of cofactors among cubes that appear on function outputs. Accordingly, it can be considered a multilevel logic optimization technique for reversible circuits. In particular, the suggested approach can efficiently implement any n -input, m -output lookup table (LUT) by a reversible circuit. This problem has interesting applications in the Shor's number-factoring algorithm and in quantum walk on sparse graphs. Simulation results reveal that the proposed cofactor-sharing synthesis algorithm has a significant impact on reducing the size of modular exponentiation circuits for Shor's quantum factoring algorithm, oracle circuits in quantum walk on sparse graphs, and the well-known MCNC benchmarks.

Quantum Logic

10.1145/2629524

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Citations (3)

データセンターに対するaチップパラダイムにおける電力を意識した仮想マシンマッピング【Powered by NICT】

IEEE Conference Proceedings (2016)

Lin Xue Xue Yuankun Bogdan Paul Wang Yanzhi Garg Siddharth

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High-Radix Design of a Scalable Montgomery Modular Multiplier With Low Latency

IEEE Transactions on Computers (2022)

Bo Zhang Zeming Cheng Massoud Pedram

The proposed herein is a scalable high-radix (i.e.,

$2^m$

) Montgomery Modular (MM) Multiplication circuit replacing the integer multiplications in each iteration of the Montgomery MM algorithm (related to the product of

$m$

bits of the multiplier and the multiplicand) with carry-save compressions and completely eliminating costly multiplications. Furthermore, the proposed Montgomery MM decomposes the multiplicand itself using a radix of

$2^w$

with

$w\geq 2m$

w≥2m

, thereby achieving a scalable design, which can deliver an issue latency of one cycle and a cycle (count) latency of

$O(N^2/(wmp))$

O(N2/(wmp))

where

$p$

denotes the number of available processing elements, each of which is designed to complete the above iteration by computing in part the product of

$w$

bits of the multiplicand and

$m$

bits of the multiplier. The area complexity of the proposed Montgomery MM is

$O(wmp)$

O(wmp)

, and thus, the Area-Latency-Product complexity is

$O(N^{2})$

O(N2)

10.1109/tc.2021.3052999

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Citations (17)

Canonical form based boolean matching and symmetry detection in logic synthesis and verification

Massoud Pedram Afshin Abdollahi

Boolean matching algorithms have many applications in logic synthesis especially in technology mapping and combinational logic verification. Canonical form based Boolean matching has been studied by many researchers. However, none of the previous work has produced in an algorithm with reasonable space and time complexities for general Boolean matching problem. In contrast, this dissertation provides an efficient and compact canonical form for representing the set of all Boolean functions that are equivalent under permutation of input variables and complementation of input or output variables (i.e., NPN-equivalent Boolean functions). In particular, important properties of the proposed canonical form are investigated, and subsequently utilized to devise an effective algorithm for computing the proposed canonical form. The low average computational complexity of this algorithm allows it to be applied to large complex Boolean functions with no limitation on the number of input variables as opposed to previous approaches, which are not capable of handling functions with more than seven inputs. Key contributions of this thesis include the introduction of the complete set of generalized signatures of a Boolean function, development of efficient methods of recognizing variable symmetries, and presentation of a proficient algorithm for computing the canonical form of the class of NPN-equivalent Boolean functions based on the generalized signatures and variable symmetries.

Standard Boolean model

Product term

Boolean network

Parity function

Maximum satisfiability problem

Boolean domain

Boolean data type

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BRDS: An FPGA-based LSTM Accelerator with Row-Balanced Dual-Ratio Sparsification

arXiv (Cornell University) (2021)

Seyed Abolfazl Ghasemzadeh Erfan Bank-Tavakoli Mehdi Kamal Ali Afzali‐Kusha Massoud Pedram

In this paper, first, a hardware-friendly pruning algorithm for reducing energy consumption and improving the speed of Long Short-Term Memory (LSTM) neural network accelerators is presented. Next, an FPGA-based platform for efficient execution of the pruned networks based on the proposed algorithm is introduced. By considering the sensitivity of two weight matrices of the LSTM models in pruning, different sparsity ratios (i.e., dual-ratio sparsity) are applied to these weight matrices. To reduce memory accesses, a row-wise sparsity pattern is adopted. The proposed hardware architecture makes use of computation overlapping and pipelining to achieve low-power and high-speed. The effectiveness of the proposed pruning algorithm and accelerator is assessed under some benchmarks for natural language processing, binary sentiment classification, and speech recognition. Results show that, e.g., compared to a recently published work in this field, the proposed accelerator could provide up to 272% higher effective GOPS/W and the perplexity error is reduced by up to 1.4% for the PTB dataset.

Pruning

Perplexity

Speedup

10.48550/arxiv.2101.02667

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Citations (8)