Yuan Taur

University of California, San Diego

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T.H. Ning

IBM Research - Thomas J. Watson Research Center

Bo Yu

GlobalFoundries (Singapore)

H.‐S. Philip Wong

Stanford University

J.Y.-C. Sun

Taiwan Semiconductor Manufacturing Company (Taiwan)

D.J. Frank

IBM (United States)

B. Davari

IBM (United States)

Yuan Yu

Sichuan Cancer Hospital

P.M. Asbeck

University of California, San Diego

Paul C. McIntyre

Stanford University

P. L. Richards

University of California, Berkeley

Cooperative Institutions

IBM (United States)

160

IBM Research - Thomas J. Watson Research Center

140

University of California, San Diego

Institute of Electrical and Electronics Engineers

University of California, Berkeley

Stanford University

University of California System

Institut polytechnique de Grenoble

Taiwan Semiconductor Manufacturing Company (Taiwan)

University of California, Santa Barbara

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Progress on millimeter wave Josephson junction mixers

AIP conference proceedings (1978)

Yuan Taur A. R. Kerr

Preset, recyclable Nb point contacts are tested as low‐noise Josephson mixers at a signal frequency of 115 GHz. The best result achieved is a mixer noise temperature (single sideband) of 120 K with unity conversion efficiency (SSB) for a junction at 6 K. Variation of mixer properties with temperature and other parameters is presented.

Electronic mixer

Compatible sideband transmission

Noise temperature

Frequency mixer

Extremely high frequency

SIGNAL (programming language)

10.1063/1.31348

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Citations (1)

On the scaling limit of ultrathin SOI MOSFETs

IEEE Transactions on Electron Devices (2006)

Wei-Yuan Lu Yuan Taur

In this paper, a detailed study on the scaling limit of ultrathin silicon-on-insulator (SOI) MOSFETs is presented. Due to the penetration of lateral source/drain fields into standard thick buried oxide, the scale-length theory does not apply to thin SOI MOSFETs. An extensive two-dimensional device simulation shows that for a thin gate insulator, the minimum channel length can be expressed as L/sub min//spl ap/4.5(t/sub Si/+(/spl epsiv//sub Si///spl epsiv//sub I/)t/sub I/), where t/sub Si/ is the silicon thickness, and /spl epsiv//sub I/ and t/sub I/ are the permittivity and thickness of the gate insulator. With t/sub Si/ limited to /spl ges/ 2 nm from quantum mechanical and threshold considerations, a scaling limit of L/sub min/=20 nm is projected for oxides, and L/sub min/=10 nm for high-/spl kappa/ dielectrics. The effect of body doping has also been investigated. It has no significant effect on the scaling limit.

Scaling limit

High-κ dielectric

10.1109/ted.2006.871879

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Citations (54)

Design of Tunneling Field-Effect Transistors Based on Staggered Heterojunctions for Ultralow-Power Applications

IEEE Electron Device Letters (2010)

Lingquan Wang Edward T. Yu Yuan Taur P.M. Asbeck

This letter presents the design of a tunneling FET with III-V-based tunnel heterojunctions for operation in digital circuits with supply voltages as low as 0.3 V. A representative implementation is predicted to achieve an on-state current drive of 0.4 mA/¿m with an off-state current of 50 nA/¿m. Comparison with homojunction counterparts reveals that the hetero-tunnel-junction implementations may address better the design tradeoff between on-state drive and off-state leakage.

Homojunction

Tunnel field-effect transistor

Tunnel junction

Leakage (economics)

10.1109/led.2010.2044012

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Citations (133)

25 nm CMOS design considerations

Yuan Taur C. Wann D.J. Frank

This paper explores the limit of bulk (or partially-depleted SOI) CMOS scaling. A feasible design for 25 nm (channel length) CMOS, without continued scaling of oxide thickness and power supply voltage, is presented. A highly 2D nonuniform profile (super-halo) is shown to yield low off-currents while delivering a significant performance advantage for a 1.0 V power supply. Several key issues, including source-drain doping requirements, band-to-band tunneling, and poly depletion effects, are examined and quantified. It is projected, based on Monte-Carlo simulations, that the delay performance of 25 nm CMOS is 3/spl times/ higher than 100 nm CMOS, and that the nFET f/sub T/ exceeds 250 GHz.

Semiconductor device modeling

10.1109/iedm.1998.746474

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Citations (237)

A 2D analytical model for SCEs in MOSFETs with high-kgate dielectric

Semiconductor Science and Technology (2010)

Qian Xie Jun Xu Tian‐Ling Ren Yuan Taur

In this paper, a two-dimensional (2D) analytical potential model for MOSFETs with high-k gate dielectric is derived based on solving a boundary value problem with 2D Poisson's equation. A novel approach to estimate short-channel threshold voltage (VT) roll-off analytically is also presented and an explicit expression for the short-channel VT roll-off is obtained. Results show that the minimum surface potential along the channel, the inverse slope of subthreshold current, short-channel VT roll-off and drain-induced barrier lowering (DIBL) predicted by the analytical model are in close agreement with 2D numerical simulation (TCAD Sentaurus) without any fitting parameters even down to a sub-20 nm channel length. This model offers a physical insight into short-channel effects and how each of the parameters of a MOSFET quantitatively impacts on ΔVT and other key features of the device. It also serves for compact modeling of high-k gate dielectric MOSFETs.

Subthreshold conduction

Drain-induced barrier lowering

Subthreshold slope

Poisson's equation

Channel length modulation

Short-channel effect

High-κ dielectric

10.1088/0268-1242/25/3/035012

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Citations (16)

Reduction of TFET OFF-Current and Subthreshold Swing by Lightly Doped Drain

IEEE Transactions on Electron Devices (2016)

Jianzhi Wu Yuan Taur

This brief models the effect of lightly doped drain on the I _ds -V _gs and I _ds -V _ds characteristics of tunnel FETs. It is shown that an extended drain depletion region can greatly reduce both the off-current and the subthreshold swing with essentially no impact on the on-current. In particular, a lightly doped drain mitigates the undesirable ambipolar effect that cannot otherwise be relieved by lengthening the channel length. However, if the density of states is not sufficiently low, a low drain doping could result in a nondegenerate condition in which the tunneling window is blocked at V _ds = 0, degrading the linear region current.

Ambipolar diffusion

Subthreshold conduction

10.1109/ted.2016.2577589

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Citations (63)

A half-micron CMOS logic generation

IBM Journal of Research and Development (1995)

Charles W. Koburger William F. Clark J. Adkisson E.L. Adler P.E. Bakeman

During the early 1990s, half-micron lithography was demonstrated in 16Mb DRAM fabrication. Utilization of this capability for CMOS logic devices within IBM followed with a trio of programs, each with different performance, density, feature list, and schedule. The first version melded 3.3/3.6-V 16Mb DRAM MOSFET devices with an improved version of an existing dense, planar, reliable multilevel back-end-of-line (BEOL) metallization and wiring technology. Since it was built directly from existing technologies, it was released quite quickly. A 3.3-V follow-on technology was added several months later. This logic offering added a local interconnect and a faster device. A second follow-on achieved greater speed improvement, calling upon a 2.5-V power supply and very tight channel-length control to obtain performances 50% above previous-generation standards, at lower power.

Dram

IBM

10.1147/rd.391.0215

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Citations (41)

Evolution of the MOSFET

Yuan Taur

This article traces the historical progress made in the metal-oxide-semiconductor field-effect transistor (MOSFET) structure as it advanced from the rudimentary micron scales to today's nanometer complementary metal-oxide-semiconductor. The timeline is partitioned into three periods: before 1980, from 1980 to 2000, and after 2000. In each period, major changes in the MOSFET process and device structure are outlined. The performance benefits derived from these evolutionary steps are highlighted.

Time line

10.1002/9781394202478.ch10

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Citations (0)

Ballistic-diffusive equations for multidimensional nanoscale heat conduction

Proceeding of International Heat Transfer Conference 9 (2002)

Ronggui Yang Gang Chen Yuan Taur

Heat equation

10.1615/ihtc12.4170

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Citations (5)

A non-GCA model for ground-plane MOSFETs