The co-packaging of optics and electronics provides a potential path forward to achieving beyond 50 Tbps top of rack switch packages. In a co-packaged design, the scaling of bandwidth, cost, and energy is governed by the number of optical transceivers (TxRx) per package as opposed to transistor shrink. Due to the large footprint of optical components relative to their electronic counterparts, the vertical stacking of optical TxRx chips in a co-packaged optics design will become a necessity. As a result, development of efficient, dense, and wide alignment tolerance chip-to-chip optical couplers will be an enabling technology for continued TxRx scaling. In this paper, we propose a novel scheme to vertically couple into standard 220 nm silicon on insulator waveguides from 220 nm silicon nitride on glass waveguides using overlapping, inverse double tapers. Simulation results using Lumerical's 3D Finite Difference Time Domain solver solver are presented, demonstrating insertion losses below -0.13 dB for an inter-chip spacing of 1 $μ$m, 1 dB vertical and lateral alignment tolerances of approximately $\pm$ 2.7 $μ$m, a greater than 300 nm 1 dB bandwidth, and 1 dB twist and tilt tolerance of approximately 2.3 degrees and 0.4 degrees, respectively. These results demonstrate the potential of our coupler for use in co-packaged designs requiring high performance, high density, CMOS compatible out of plane optical connections.
An experimentally demonstrated, vertical chip-to-chip evanescent coupler between silicon nitride (Si₃N₄) and silicon (Si) is presented with the coupler loss measured to be 0.39 ± 1.06 dB at 1550 nm with a 1-dB bandwidth of 160 nm extending across the C-band, S-band, and L-band (1480-1640 nm). The average coupling loss was determined to be 0.73 dB for the 1480-1640 nm wavelength range with a ± 2σ tolerance of ± 0.92 dB. The 1-dB lateral alignment tolerance was 1.56 ± 0.14 μm at 1550 nm and the average tolerance was 1.38 ± 0.24 μm across the 1480-1640 nm wavelength regime. In addition, the average coupling loss varied by less than ± 0.35 dB and the average 1-dB alignment tolerance varied by less than ± 30 nm for temperatures varying from 23-60°C. Finally, the average coupling loss range was less than 1.5 dB range across four sets of identically packaged die. This is the first experimental demonstration of an inter-chip, passively assembled evanescent coupler using standard CMOS foundry processes for directly coupling between Si and Si₃N₄, overcoming a waveguide refractive index difference of Δn = 1.32 without requiring taper tip widths of less than 100 nm.
MassTech Collaborative has helped to make the Commonwealth of Massachusetts a beacon for advanced manufacturing. In partnership with the AIM Photonics manufacturing institute, MassTech has launched five Laboratories for Education and Application Prototypes (LEAPs) within academic institutions spread widely across Massachusetts, to develop a skilled workforce in integrated photonics. Hands-on and in-person workshops, bootcamps and laboratory courses are offered at these LEAPs to learners from academia, industry, and the government. The MA LEAP network stands as an excellent self-sustaining model for hands-on STEM education and workforce training for the rest of the country.
MassTech Collaborative has helped to make the Commonwealth of Massachusetts a beacon for advanced manufacturing. In partnership with the AIM Photonics manufacturing institute, MassTech has launched five Laboratories for Education and Application Prototypes (LEAPs) within academic institutions and/or companies spread across Massachusetts, to develop a skilled workforce in integrated photonics. Hands-on and in-person workshops, bootcamps and laboratory courses are offered at these LEAPs to learners from academia, industry, and the government. The MA LEAP network stands as an excellent self-sustaining model for hands-on STEM education and workforce training for the rest of the country.
An experimentally demonstrated, vertical chip‐to‐chip evanescent coupler between silicon nitride (SiN) and silicon (Si) is presented with the coupler loss measured to be 0.39 1.06 dB at 1550 nm with a 1‐dB bandwidth of 160 nm extending across the C‐band, S‐band, and L‐band (1480–1640 nm). The average coupling loss is determined to be 0.73 dB for the 1480–1640 nm wavelength range with a 2 σ tolerance of 0.92 dB. The 1‐dB lateral alignment tolerance is 1.56 0.14 μm at 1550 nm and the average tolerance is 1.38 0.24 μm across the 1480–1640 nm wavelength regime. In addition, the average coupling loss varies by less than 0.35 dB and the average 1‐dB alignment tolerance varies by less than 30 nm for temperatures varying from 23 to 60 °C. Finally, the average coupling loss range is less than 1.5 dB range across four sets of identically packaged die. This is the first experimental demonstration of an interchip, passively assembled evanescent coupler using standard complementary metal‐oxide‐semiconductor foundry processes for directly coupling between Si and SiN, overcoming a waveguide refractive index difference of = 1.32 without requiring taper tip widths of less than 100 nm.
3D printed free-form couplers and inverse tapers are two different vertical integration strategies for coupling light between a PIC and glass interposer. For the free-form coupling scheme, 5×5×0.5 mm 3 dummy silicon dies are bonded to a glass substrate using solder bumps via flip-chip bonding. The gap distance between the bonded chips is controlled by the solder height based on various bond pad sizes. An array of 14×14 square gold bond pads on the silicon chip is used with the bond pad length varying from 50 μm to 105 μm in order to maintain a required height. SAC305 solder is jetted onto the bond pads and an optimization of the reflow profile is performed to achieve defect-free, and high-wetting solder bumps. For the inverse taper coupling approach, the PIC is bonded to glass using a UV-curable optical epoxy (n=1.5). The measured vertical distance falls within the 2.8 μm required Z-tolerance for evanescent coupling according to simulation.
An experimentally demonstrated, vertical chip-to-chip evanescent coupler between silicon nitride (Si₃N₄) and silicon (Si) is presented with the coupler loss measured to be 0.39 ± 1.06 dB at 1550 nm with a 1-dB bandwidth of 160 nm extending across the C-band, S-band, and L-band (1480-1640 nm). The average coupling loss was determined to be 0.73 dB for the 1480-1640 nm wavelength range with a ± 2σ tolerance of ± 0.92 dB. The 1-dB lateral alignment tolerance was 1.56 ± 0.14 μm at 1550 nm and the average tolerance was 1.38 ± 0.24 μm across the 1480-1640 nm wavelength regime. In addition, the average coupling loss varied by less than ± 0.35 dB and the average 1-dB alignment tolerance varied by less than ± 30 nm for temperatures varying from 23-60°C. Finally, the average coupling loss range was less than 1.5 dB range across four sets of identically packaged die. This is the first experimental demonstration of an inter-chip, passively assembled evanescent coupler using standard CMOS foundry processes for directly coupling between Si and Si₃N₄, overcoming a waveguide refractive index difference of Δn = 1.32 without requiring taper tip widths of less than 100 nm.
'/%3e%3cpath d='M200 752.362h200v300H200z' style='fill:%23fff;fill-opacity:1;stroke:none' transform='translate(0 -752.362)'/%3e%3cpath d='M400 752.362h200v300H400z' style='fill:%23ff883e;fill-opacity:1;stroke:none' transform='translate(0 -752.362)'/%3e%3c/svg%3e)
'%3e%3cpath fill='%23012169' d='M0 0v30h60V0z'/%3e%3cpath stroke='%23fff' stroke-width='6' d='m0 0 60 30m0-30L0 30'/%3e%3cpath stroke='%23C8102E' stroke-width='4' d='m0 0 60 30m0-30L0 30' clip-path='url(%23b)'/%3e%3cpath stroke='%23fff' stroke-width='10' d='M30 0v30M0 15h60'/%3e%3cpath stroke='%23C8102E' stroke-width='6' d='M30 0v30M0 15h60'/%3e%3c/g%3e%3c/svg%3e)