T.L. Savarino

Cadence Design Systems (United States)

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P.R. O'Brien

Digital Wave (United States)

James M. Pierce

Genomics Institute of the Novartis Research Foundation

John L. Wyatt

Massachusetts Institute of Technology

E. Tuncer

Google (United States)

S. Y. Kim

The University of Texas at Austin

L.T. Pillage

The University of Texas at Austin

B. Krauter

IBM (United States)

Rohini Gupta

Cornell University

Dean P. Neikirk

The University of Texas at Austin

Cooperative Institutions

The University of Texas at Austin

IBM (United States)

Digital Wave (United States)

University of California, Berkeley

IBM Research - Austin

Google (United States)

TiGenix (Spain)

Software and Engineering Associates (United States)

Genomics Institute of the Novartis Research Foundation

John Jay College of Criminal Justice

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Fast on-chip delay estimation for cell-based emitter coupled logic

1993 IEEE International Symposium on Circuits and Systems (2003)

P.R. O'Brien John L. Wyatt T.L. Savarino James M. Pierce

An effort was made to produce fast, but accurate, estimates of best and worst-case delay for on-chip emitter-coupled logic (ECL) nets. The effort consisted of two major parts: (1) macromodeling of ECL logic gates acting as both sources and loads; and (2) delay estimation for individual nets using the gate macromodel parameters and RC tree models for metal interconnect. Both of these functions have been extensively tested on an industrial ECL process and cell (i.e., logic gate) library. It is noted that the success of a macromodeling approach relies on repetitive use of members of a library of modeled cells. A fixed computational cost (several CPU hours per cell) is paid to obtain simplified macromodel parameter values. Resultant timing estimates are typically within 5-10% of SPICE and are obtained roughly three orders of magnitude more quickly than SPICE.< >

Spice

Tree (set theory)

Logic level

Emitter-coupled logic

10.1109/iscas.1988.15180

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Citations (10)

Fast On-Chip Delay Estimation For Cell-Based Emitter Coupled Logic

Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE (1988)

P.R. O'Brien John L. Wyatt T.L. Savarino James M. Pierce

The goal of this work is to produce fast, but accurate, estimates of best and worst case delay for on-chip emitter coupled logic (ECL) nets. The work consists of two major parts: 1) macromodelling of ECL logic gates acting as both sources and loads; and 2) delay estimation for individual nets using the gate macromodel parameters and RC tree models for metal interconnect. Both of the above functions (gate macromodelling and delay estimation) have been extensively tested on an industrial ECL process and.cell (i.e., logic gate) library. The success of a macromodelling approach relies on repet-itive use of members of a library of modelled cells. A "fixed" computational cost (several c.p.u. hours per cell) is paid to obtain simplified macromodel parameter values. Resultant timing estimates are typically within 5-10% of SPICE [1] and are obtained roughly three orders of magnitude more quickly than SPICE.

Spice

Emitter-coupled logic

Logic level

10.1117/12.947454

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Citations (3)

Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation

P.R. O'Brien T.L. Savarino

An efficient algorithm is presented which accounts for series resistance by computing a reduced-order approximation for the driving-point admittance of an RC tree. The algorithm consists of four rules which allow the Taylor series expansion coefficients of the driving-point admittance looking downstream of a given point in the tree to be correctly propagated further upstream. Rules 1-3 involve movement upstream, along a single branch, and past, respectively, a lumped capacitor to ground, a series lumped resistor, and a uniformly distributed RC segment. Rule 4 involves combining two or more different admittance expansions in parallel at a branch point in the tree. Using an emitter-coupled-logic clock buffer as an example, the authors demonstrate a significant improvement in accuracy.< >

Admittance

Tree (set theory)

Resistive touchscreen

10.1109/iccad.1989.77002

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Citations (144)

Modeling the Driving-Point Characteristic of Resistive Interconnect for Accurate Delay Estimation

Springer eBooks (2003)

P.R. O'Brien T.L. Savarino

Elmore delay

Admittance

Tree (set theory)

Resistive touchscreen

Equivalent series resistance

Spice

10.1007/978-1-4615-0292-0_31

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Citations (219)

Efficient on-chip delay estimation for leaky models of multiple-source nets

P.R. O'Brien T.L. Savarino

An algorithm for efficiently computing an Elmore approximation in a leaky RC tree which may contain any number of uniformly distributed RC segments is presented. This algorithm works in the frequency domain, and it owes much of its efficiency to the fact that intermediate results leftover from computation of the driving-point admittance approximation are reused. The algorithm for computing an Elmore approximation starts at the output of the active source gate and proceeds downstream, in a finite sequence of steps, to the input of a specified load gate.< >

Tree (set theory)

Sequence (biology)

Admittance

10.1109/cicc.1990.124700

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Citations (20)

An efficient methodology for extraction and simulation of transmission lines for application specific electronic modules

International Conference on Computer Aided Design (1993)

S. Y. Kim E. Tuncer Rohini Gupta B. Krauter T.L. Savarino

Physical interconnect introduces new challenges for parameter extraction and delay calculation for application specific electronic module (ASEM) design automation. Efficiency dictates the precharacterization of extracted electrical parameters in the same manner as application specific integrated circuits (ASICs). However, ASEM interconnect is dominated by frequency dependent LC propagation which makes precharacterization difficult for all possible configurations. Moreover, simulating the transient behavior of the ASEM interconnect for noise and delay analysis requires the combined use of a variety of models and techniques for efficiently handling lossy, low-loss, frequency dependent, and coupled transmission lines together with lumped parasitic elements. We propose to use conformal mapping to generate abstracted models for the electrical parameters of various RLC interconnect cross-sections, including the frequency dependence caused by ground plane proximity and skin effects. Along with precharacterized lumped parasitic elements and nonlinear driver and load models, these models are simulated using a generalized time-domain macromodeling approach that can combine different types of transmission line analysis in one simulation environment. An automatic selection mechanism is derived for determination of the best time-domain macromodel for a particular distributed segment.

Parasitic extraction

RLC circuit

Ground plane

Lossy compression

10.5555/259794.259804

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Citations (13)