F. Okuda

Mitsubishi Group (Japan)

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S. Komori

Renesas Electronics (Japan)

H. Shimano

Tokyo University of Pharmacy and Life Sciences

Kazuo Kyuma

Council for Science, Technology and Innovation

K. Shimomura

Toyota Technological Institute

N. Sakashita

Mitsubishi Electric (Japan)

Haruhiko Abe

University of Occupational and Environmental Health Japan

A. Yasuoka

Sapporo City University

S. Yamakawa

Mitsubishi Electric (Japan)

Tetsuo Tada

Tokushima Bunri University

S. Baba

Cooperative Institutions

Mitsubishi Group (Japan)

Mitsubishi Electric (Japan)

Mitsubishi Electric (Germany)

Mitsubishi Corporation (United States)

Renesas Electronics (United States)

Mitsubishi Electric (United States)

Osaka University

Renesas Electronics (Japan)

Waseda University

Kyushu Institute of Technology

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A built-in self-test circuit with timing margin test function in a 1 Gbit synchronous DRAM

N. Sakashita F. Okuda K. Shimomura H. Shimano M. Hamada

This paper describes the implementation of a BIST circuit with timing margin test functions to a 200 MHz 1 Gbit synchronous DRAM. 220 ps-resolution timing signals with up to 80 ns cycle time are generated by a phase-locked loop (PLL) circuit and a delayed timing generator. These timing signals are used not only as actual control signals but also as reference signals in an AC timing comparator. The entire BIST circuit, which includes 20/spl times/4 bit LFSRs, occupies only 0.8% of the chip area. A cost evaluation of the BIST shows that the technology is effective for 64 Mbit high-speed DRAMs and beyond.

Dram

Margin (machine learning)

Gigabit

Built-in self-test

10.1109/test.1996.556977

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Citations (16)

A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture

IEEE Journal of Solid-State Circuits (1996)

N. Sakashita Y. Nitta K. Shimomura F. Okuda H. Shimano

This paper describes key techniques for a 1.6-GB/s high data-rate 1-Gb synchronous DRAM (SDRAM). Its high data transfer rate and large memory capacity are targeted to the advanced unified memory system in which a single DRAM (array) is used as both the main memory and the three-dimensional (3-D) graphics frame memory in a time sharing fashion. The 200-MHz high-speed operation is achieved by the unique hierarchical square-shaped memory block (SSMB) layout and the novel distributed bank (D-BANK) architecture. A 0.29 /spl mu/m/sup 2/ cell and 581.8 mm/sup 2/ small die area are achieved using 0.15-/spl mu/m CMOS technology. The /spl times/61 chip uses 196-pin BGA type chip-scale-package (CSP). Implementation of a built-in self-test (BIST) circuit with a margin test capability is also described.

Dram

Dynamic random-access memory

Memory architecture

10.1109/jssc.1996.542309

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Citations (23)

A 1.6 GB/s data-rate 1 Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture

Y. Nitta N. Sakashita K. Shimomura F. Okuda H. Shimano

This paper describes key technologies for a 1.6 GB/s high bandwidth 1 Gb synchronous DRAM (SDRAM). Its high data transfer rate and large memory capacity are intended for a unified memory system in which a single DRAM (array) is time-shared as both main memory and 3D graphics frame memory. 200 MHz operation is achieved by the hierarchical square-shaped memory block (SSMB) layout and the distributed bank (D-BANK) architecture. A built-in self-test (BIST) circuit with margin-test capability is included.

Dram

Memory architecture

Memory bandwidth

10.1109/isscc.1996.488724

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Citations (14)