Summary form only given. The output characteristics (I/sub DS/ vs. V/sub DS/) of thin-film SOI MOSFETs show a decrease in drain current for increasing drain-source voltage at high power densities. In addition, the pinch-off point is shifted for small channel length, an effect inconsistent with theory due to the suppression of the body effect in these transistors. In an investigation of these phenomena it was found that both the negative resistance and the movement of the pinch-off point arise from a degradation of mobility caused by local heating due to power dissipation in the channel. This is a result of the poor thermal conductivity of the buried oxide; a worst case is that of a thin-film transistor on a thick buried insulator.< >
A full adder is used to demonstrate a programming technique using binary functionality for increased functional density in quaternary look-up table-based field programmable gated arrays (FPGAs). The potential inefficiencies of using quaternary level functionality for these architectures are also illustrated.
Increased use of machine vision systems is making a significant contribution to ensuring competitiveness in modern manufacturing. However, the multi-disciplinary nature of machine vision necessitates a high level of competence in a diverse range of subjects. These factors have resulted in a shortage of qualified machine vision engineers. Overcoming this skills shortage can be approached in two ways; the education of more machine vision engineers or a reduction in the time taken to design and implement a machine vision system. One possible solution to both these problems is the use of an intelligent design tool that will aid an engineer in designing a complete machine vision system. This work focuses on one component of such a tool, a hybrid intelligent system to aid in the selection of algorithms for use in a particular machine vision task. The approach taken in this work belongs to the more general category of systems for the intelligent supervision of a library of operators and as such can be generalized to other applications and domains. The system design is based around an evolutionary algorithm (EA), case based reasoning (CBR) and rule based reasoning (RBR) architectures.
A novel low cost interconnected architecture (LCIA) is proposed in this paper, which is an efficient solution for the neuron interconnections for the hardware spiking neural networks (SNNs). It is based on an all-to-all connection that takes each paired input and output nodes of multi-layer SNNs as the source and destination of connections. The aim is to maintain an efficient routing performance under low hardware overhead. A Networks-on-Chip (NoC) router is proposed as the fundamental component of the LCIA, where an effective scheduler is designed to address the traffic challenge due to irregular spikes. The router can find requests rapidly, make the arbitration decision promptly, and provide equal services to different network traffic requests. Experimental results show that the LCIA can manage the intercommunication of the multi-layer neural networks efficiently and have a low hardware overhead which can maintain the scalability of hardware SNNs.
Modern computing systems are using Networkson-Chip (NoCs) for scalable on-chip communications. Traditional security attacks have focused on the computing cores however modern attacks can focus on the NoC interconnect as a means to injecting unwanted traffic. This poses a significant security risk to physical systems that rely on sensory feedback and control signals. Malicious modification of these signals generates abnormal traffic patterns which affect the operation of the system and its performance. In this paper, we aim to identify abnormal traffic patterns (attacks) in Networks-on-Chip data through the use of Spiking Neural Networks. We explore the vulnerabilities of Denial-of-Service (DoS) attacks and report on evaluations to identify the impact of the duration of individual attacks on the rate of detection.
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