A combination of simulation, resist modification and process optimization were used to develop production worthy dry 193nm lithography processes, suitable for the metal trench layers of 65nm node logic devices. The important performance characteristics of a back-end metal trench layer are through-pitch proximity bias, lithographic latitude and ultimate resolution. Simulation results suggested that a moderate annular illumination setting balances proximity bias against resolution at the forbidden pitch, yielding a good overall through-pitch common process window. Resist material optimization through resin, PAG (photo-acid generator) and base quencher modification improves proximity bias and results in excellent lithographic performances of good LER (line edge roughness), low MEF (Mask Error Factor) and wider process latitude. To investigate extendibility to 45nm node applications, the immersion compatibility of the optimized resist with several top coats are reported.
Obtaining good post-etching CD uniformity is getting more and more important in advanced processes such as 90 nm, 65 nm, and even 45nm for 300 mm wafers. But process noise greatly impacts the CD uniformity, especially etching bias and metrology noise. To achieve a CD uniformity of below 3 nm for 300 mm post-etch wafers, the metrology noise and process noise must be reduced and compensated for. In this paper, we demonstrate spectroscopic ellipsometry CD with the advantages of high stability and high accuracy to get CD information precisely, and high sensitivity to monitor PEB temperature and exposure energy fine variation in order to compensate for the etching bias. This study focuses on the feasibility of minimizing the CD uniformity of post-etch wafers by ADI CD compensation for a 300 mm leading-edge fab. Because the CD uniformity of after-development inspection (ADI) wafers from a leading-edge lithographic tool could be in the range of only 3 nm, it is very challenging to reveal the true CD signature of an ADI wafer using a metrology tool. A spectroscopic ellipsometry based metrology tool, SpectraCD, was used in this study. In order to make sure the CD signatures reported by SpectraCD reveal the true behavior of a lithographic tool, the well-published Total Test Repeatability (TTR) test was adopted. In comparison with 3 nm CD uniformity, a 0.2 nm TTR is accurate enough for this study. In addition, from more than 100 wafers produced within a week, the CD signature of ADI wafers is very stable on wafer-to-wafer and lot-to-lot bases. Basically, all the ADI wafers produced from a single post-exposure-bake plate of an exposure tool within a week show very similar CD signatures. The feasibility of reaching a CD uniformity of 3 nm for post-etch wafers will be demonstrated in this study.
As the pattern size shrinking down below 1/4 of the exposure wavelength, the NA of exposure tool has to be increased proportionally. The use of hyper NA and immersion exposure system for improving image quality may result in a small workable process window. Hence, resolution enhancement technology (RET) becomes a necessity for semiconductor manufacturing. Previous studies have demonstrated many RETs, such as CPL, DDL, IML and DPT etc. can improve the process window for different applications.1,2,3,4 In this work, we show manufacturing implementation of a 32nm node SRAM cell with different RET approaches. The diffusion, poly, contact, and metal layers were chosen as the target design. The process development project starts from the wafer exposure scheme setting, which includes the multi-exposure, illumination shape and mask type. After the RET has been specified, the process performance indexes, such as MEEF, PW, and CDU are characterized by using both simulation and empirical data. The mask design and OPC is implemented After the mask data preparation step, we then optimize exposure parameters for best printing performance and follow it by verifying actual wafer data. The mask making spec and DFM design rule constrains have been assessed and recommended for 32nm node manufacturing. Also, we have examined the immersion process defect impact and control methodology for production environment. In this paper, we report the result of optimizing RET process (including mask data generation, reticle making specifications, and wafer printing) for 32nm SRAM. With 193nm ultra high NA immersion exposure scanner (such as ASML /1900), it is capable of meeting 32nm SRAM manufacturing requirement.
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