This paper demonstrates the 32-Mb chain ferroelectric RAM (chain FeRAM) with 0.2-μm three-metal CMOS technology. A small die size of 96 mm 2 and a high cell/chip area efficiency of 65.6% are realized not only by the small cell size using capacitor-on-plug technology but also by two key techniques that utilize the three-metal process: 1) a compact memory cell block structure that eliminates plateline area and reduces block selector area and 2) the segment/stitch array architecture which reduces the area of row decoders and plate drivers. As a result, the average cell size shrinks to 1.875 μm 2 , which is smaller than a 0.13-μm SRAM cell, and the chip size is reduced to 70% of the chain FeRAM of conventional configuration with two-metal process. Moreover, a power-on/off sequence suitable to the chain FeRAM is introduced to protect the memory cell data from the startup noise. Compatibility with low-power SRAM is a key issue for mobile applications. The low-standby-current bias generator is introduced and the standby current of the chip is suppressed to 3 μA. The modified address access mode is also adopted to eliminate the need of intentional address transition after the startup of the chip. The chip enable access time was 50 ns and cycle time was 75 ns at 3.0-V V/sub dd/.
A concept was presented for the prediction of the device lifetimes for the hot-carrier effect (hot-carrier lifetimes) in floating SOI MOSFETs. The concept is that hot-carrier lifetimes in floating SOI MOSFETs can be predicted by estimating the hole current. In order to verify the validity of this concept, the hole current was investigated using device simulation. The results showed that the ratio of the hole current to the drain current in a floating-body SOI MOSFET is approximately equal to the ratio of substrate current to drain current in a body-tied one. Based on this fact, a method for accurately predicting the hot-carrier lifetime in floating-body SOI MOSFETs was proposed. The hot-carrier lifetime predicted with this method agreed well with the experimental results. This study showed that only the drain current difference between floating and body-tied structures results in lifetime differences, and there is no special effect on hot-carrier degradation in floating SOI MOSFETs. In this prediction, therefore, floating SOI MOSFETs can be treated in the same way as bulk MOSFETs. Hot-carrier lifetimes in floating SOI MOSFETs can be predicted using the hole current, while substrate currents are used in bulk MOSFETs.
The subthreshold slope in ultra-thin-film fully depleted SOI MOSFETs is investigated for channel lengths from the long channel region down to 0.1 mu m. A doping effect is found which allows improvement of the S-factor by increasing the channel doping concentration. In order to explain this phenomenon and to clarify the mechanism of S-factor degradation at short gate lengths, a two-dimensional analytical model is developed. A modified boundary condition for the two-dimensional Poisson equation is introduced to account for the nonlinear potential distribution inside the buried oxide. It is found that the S-factor short-channel degradation is governed by three mechanisms: the rise of capacitances at the channel source and drain ends due to the two-dimensional potentional distribution; the subthreshold current flow at the back channel surface; and the modulation of the effective current channel thickness during the gate voltage swing in the subthreshold region. The analytical model results are compared to those of numerical device simulation, and a good agreement is found.< >
A gate-overlapped LDD structure was introduced to ultra-thin SOI MOSFET's in order to overcome the degradation in source-to-drain breakdown voltage (BVds) due to a parasitic bipolar action. By reductions in drain electric field and parasitic resistance at a source n/sup -/ region, the BVds was improved with almost the same current drivability as that in single drain structure. The behavior of the BVds on LDD n/sup -/ concentration was investigated by use of a numerical device simulator, and it was found that the electric field at a lower portion of the n/sup -/ region, which forms the current path, was relaxed effectively at an optimum n/sup -/ doping condition.< >
The scaling of the metal-oxide-semiconductor field-effect transistor (MOSFET) into the deep-submicron regime increases the influence of source/drain engineering, e.g. , the use of a lightly doped source and drain (LDD) structure, on the transistor subthreshold characteristics due to the two-dimensional potential distribution. Device parameters like the subthreshold slope ( S -factor) and the threshold voltage may become dependent on the LDD conditions. This paper presents a theoretical analysis of how source/drain conditions affect the short-channel behavior of fully depleted silicon-on-insulator (SOI) MOSFET's. Accurate two-dimensional analytical modeling which takes into account the non-linear potential variation inside the buried oxide helps elucidate the mechanisms involved. The results, supported by numerical device simulation, indicate that for a correct description in addition to the different built-in potential of the source and drain junctions, an increasing effective channel length with LDD doping reduction must be taken into account.
