The supervision of semiconductor power devices in operation demonstrates an obvious interest to improve the operating safety of electronic power converters used in critical applications. Unfortunately, this is a significant challenge due to the variability of stress conditions on the one hand and to the difficulty to implement accurate measurement systems in power stages on the other. Using VCE measurement as a real-time supervision method is evaluated here by using aging test results obtained on insulated gate bipolar transistor (IGBT) modules stressed by power cycling. These results are related to the aging of bond wires and metallization, on the top part of the module. Results were obtained in original test benches whose characteristics are overviewed briefly in the first part of this paper, along with a description of test conditions. The second part presents selected results extracted from a larger work and focusing on the VCE evolution with respect to degradations of the module's top part. Their analysis highlights the potential of VCE measurement. The last part proposes the principle of a specific system able to achieve real-time VCE supervision in the test benches in operation.
A suite of highly precise surface planarization equipment and associated unit process have been developed for several years. Recent studies showed that this process is suitable to address the persistent needs for improved planarity of surface topographies and bonding interfaces during advanced packaging fabrications and assembly. Myriad process capabilities have been achieved to date on both wafer-level for device die fabrications as well as on panel-level for interposer and substrate fabrications. Some planarization highlights include (i) achieving copper pillars height uniformity of less than 1.5um across entire 300mm Si low-k wafer area, (ii) being able to integrate with panel-, lamination-based RDL fabrications based on either pohto-lithography method or by direct laser patterning methods in planarizing both patterned plating features and blanket overburden layer structure, and (iii) establishing the manufacturing readiness for large panel substrate sizes.
Due to its superior electrical and thermal characteristics, silicon carbide power modules will soon replace silicon modules to be mass-produced and implemented in all-electric and hybrid-electric vehicles (HEVs). Redesign of the power modules will be required to take full advantage of these newer devices. A particular area of interest is high-temperature power modules, as under-hood temperatures often exceed maximum silicon device temperatures. This review will examine thermal packaging options for standard Si power modules and various power modules in recent all-electric and HEVs. Then, thermal packaging options for die-attach, thermal interface materials (TIM), and liquid cooling are discussed for their feasibility in next-generation silicon carbide (SiC) power modules.
The recent progress in artificial intelligence (AI) and machine learning (ML) has enabled computing platforms to solve highly complex difficult problems in computer vision, robotics, finance, security, and science. The algorithmic progress in AI/ML have motivated new research in hardware accelerators. The dedicated accelerators promise high energy efficiency compared to software solutions using CPU. However, as AI/ML models become complex, the increasing memory demands and, hence, high energy/time cost of communication between logic and memory possess a major challenge to energy efficiency. We review the potential of heterogeneous integration in addressing the preceding challenge and present different approaches to leverage heterogeneous integration for energy-efficient AI platforms. First, we discuss packaging technologies for efficient chip-to-chip communication. Second, we present near-memory-processing architecture for AI accelerations that leverages 3D die-stacking. Third, processing-in-memory architectures using heterogeneous integration of CMOS and embedded non-volatile memory are presented. Finally, the article presents case studies that integrate preceding concepts to advance AI/ML hardware platform for different application domains.
Advances in high-performance package with high I/O densities, and power modules with escalating current needs are driving the need for a new class of interconnection technologies, with thermal stability, current-carrying capability and pitch scalability beyond that of traditional solders. Solid-liquid interdiffusion (SLID or SoLID) or transient liquid phase (TLP) bonding systems, in which the bonding layer is fully converted to intermetallics, are highly sought after to extend the applicability of solders to pitches below 30μm, and for die-attachment in high-temperature high-power systems. This paper introduces an innovative SLID concept, consisting of isolating a metastable intermetallic phase between barrier layers for a faster conversion to metastable composition than that in traditional SLID. The Cu-Sn system was used for this demonstration with a designed transition to metastable Cu 6 Sn 5 instead of the stable Cu 3 Sn phase, usually targeted. The novel interconnection structure enables assembly within seconds and improved thermomechanical reliability, with all the benefits of SLID bonding such as outstanding thermal stability over 10x reflow and enhanced power handling capability with a current density of 10 5 A/cm 2 . The paper first describes the design and fabrication of the interconnection structure, including the barrier and bonding layers based on diffusion and thermomechanical modeling. Ultra-fast assembly by low-pressure thermocompression bonding was demonstrated on die-attach joints and interconnections at 100μm pitch, followed by extensive reliability characterization, including thermal stability evaluation, electromigration test, and die-shear test. The designed interconnections successfully passed JEDEC standards, qualifying this novel interconnection technology for high-temperature, high-power operations at fine-pitch.
This paper reports the use of circumferential polymer collars as a strain-relief mechanism to improve the fatigue life of low-CTE package-to-PCB solder interconnections, while preserving SMT-compatibility and reworkability. Acting as a partial underfill, the polymer-collar serves to block shear deformation at the solder-package interface, and redistributes the load to reduce the overall plastic strain concentration in the solders. It also suppresses failure initiation from defective surface sites and, thus further enhances reliability. Ultra-thin glass 100μm interposers were fabricated in 18.4 mm × 18.4 mm size to model, design and demonstrate the reliability enhancement with the polymer-collar approach. The detailed interposer design and fabrication process with laminated dielectric and metallization layers on both sides is presented. A new class of epoxies with low modulus, without the incorporation of silica fillers, was used to act as the polymer collars. The polymer collars are formed by spin-coating with an optimized thickness to provide the best compromise between the effective strain relief and reworkability. Board-level assembly was performed using standard SMT processes for glass interposers with and without polymer collars. Thermal cycling reliability testing (-40°C to 125°C) of interposers, assembled on PCBs with and without polymer collars for various thicknesses of the collar was performed.
High-bandwidth 5G and 6G communication systems will inevitably migrate to 3D package architectures with backside or embedded dies and antenna-integrated packages for ultra-low losses and smaller footprints. With the trend to such 3D millimeter-wave (mm-wave) packages, the losses from the assembly and through-vias tend to dominate the overall losses. Traditional wirebond and thick solder interconnections lead to large mm-wave interconnect losses that are not acceptable for emerging 5G and 6G communications. This paper focuses on the material syntheses and process development of nanocopper interconnections with ultra-low interconnect losses for chip-last or flip-chip assembly in packages. The first part of the paper introduces the material synthesis of an innovative copper paste with shorter sintering times and temperatures. Optimized conditions are obtained to attain a conductivity of 1.4×10 7 S/m. This is equivalent to 82% increase in conductivity compared to that of solder. The surface roughness is also measured through atomic-force microscopy. Results suggest that the copper paste features higher roughness than that of solders. The second part of this paper discusses the potential of novel nanocopper paste to replace solders as a package assembly material, focusing on the effect of the conductivity and surface roughness with regard to the insertion loss in interconnection bumps. Based on the improved material properties of nanocopper paste, the model shows a 53% reduction in the dB scale at 28 GHz, by employing nanocopper paste. Die shear test for copper paste is also performed to show a high potential to replace solders as a flip-chip assembly material in both printed-circuit-board and mm-wave packaging technologies.
One constant in electronic system integration is the continuous trend towards smaller devices with increased functionality, driven by emerging mobile and high-performance applications. This brings the need for higher bandwidth at lower power, translating into increased I/O density, to enable highly-integrated systems with form factor reduction. These requirements result in the necessity of interconnection pitch-scaling, below 30 μm in the near future, and substrates with high wiring densities, leading to routing with sub 5 μm L/S where standard surface finishes (ENIG, ENEPIG) are no longer applicable. Copper pillar with solder caps technology is currently the prevalent solution for off-chip interconnections at fine pitch, dominating the high performance and mobile market with pitches as low as 40 μm in production. However, this technology faces many fundamental limitations in pitch scaling below 30 μm, due to solder bridging, IMC-solder interfacial stress management, and poor power handling capability of solders. All-copper interconnections without solder are very sought after by the semiconductor industry and have been applied to 3D-IC stacking, however no cost effective, manufacturable and scalable solution has been proposed to date for HVM and application to non CTE matched package structures. The low temperature Cu-Cu interconnection technology without solder recently patented by Georgia Tech PRC is one of the most promising solutions to this problem. The main bottleneck of copper oxidation is dealt with by application of ENIG on the Cu bumps and pads, enabling formation of a reliable metallurgical bond by thermocompression bonding (TCB) at temperatures below 200°C, in air, with cycle-times compatible with HVM targets. However, to ensure a bump collapse of 3 μm to overcome non-coplanarities and warpage, a pressure of 300MPa is used in the Process-of-Record (PoR) conditions, limiting the scalability of this technology. This paper introduces a novel Electroless Palladium / Autocatalytic Gold (EPAG) surface finish process, to enable the next generation of high density substrates and interconnections. With circa 100nm-thin Pd and Au layers, the EPAG finish can be applied to fine L/S wiring, with no risk of bridging adjacent Cu traces, even with spacing below 5 μm. Further, the EPAG finish is compatible with current interconnection processes; such as wire bonding, and the Cu pillar and solder cap technology for fine-pitch applications. For further pitch reduction, the EPAG surface finish was coupled to GT PRC's low-temperature Cu-interconnections, in an effort to reduce the bonding load for enhanced manufacturability without degrading the metallurgical bond or reliability. This paper is the first demonstration of such interconnections. The effect of the surface finish thickness and composition on the bonding load, assembly yield, quality of the metallurgical bond was extensively evaluated based on analysis of the metal interface microstructures and the chemical composition of the joints. The current PoR using Electroless Nickel / Immersion Gold (ENIG) coated Cu pillars and pads was used as reference. A novel surface finish is introduced, which allows formation of Cu-Cu interconnections without solder at lower pressure, between a silicon die and glass, organic or silicon substrate at fine pitch, allowing the performance improvements demanded by the IC Packaging Industry.
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