Suhaib A. Fahmy

University of Warwick

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Shanker Shreejith

Trinity College Dublin

Kizheppatt Vipin

Birla Institute of Technology and Science, Pilani - Goa Campus

Martin Lukasiewycz

Robert Bosch (Germany)

Douglas L. Maskell

Nanyang Technological University

Samarjit Chakraborty

University of North Carolina Health Care

Abhishek Kumar Jain

Xilinx (United States)

Sebastian Steinhorst

Technical University of Munich

Philipp Mundhenk

Robert Bosch (Germany)

Linda Doyle

Trinity College Dublin

Ian McLoughlin

University of Science and Technology of China

Cooperative Institutions

Nanyang Technological University

Trinity College Dublin

King Abdullah University of Science and Technology

Imperial College London

University of Warwick

University of California, Berkeley

Technical University of Munich

Intel (United States)

University College Dublin

Xilinx (United States)

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Welcome Message

Brendan Farley Patrick Dorsey Vivienne Sze Dan Werthimer Marilyn Wolf

We are delighted to host FPL2018 here in Trinity College Dublin.In its 28th incarnation, FPL continues to be a leading forum for exhibiting the latest in reconfigurable computing.The programme reflects not only the diversity of applications in the area but also the breadth of industry involvement with many of our sponsors exhibiting, presenting and helping to make the event a success.The keynotes are balanced between academia and industry and we are pleased to be welcoming such a prestigious selection of role models to speak to us this year.At FPL2018 we undertook to improve the gender balance in the organisation of the conference and we are glad to report that half of the keynote speakers and 67% of the programme chairs are women.This year we received 236 submissions in total (about the same as 2017), including 17 Ph.D. forum and demo night submissions.

Incarnation

10.1109/fpl.2018.00005

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Mapping Time-Critical Safety-Critical Cyber Physical Systems to Hybrid FPGAs

Kizheppatt Vipin Shanker Shreejith Suhaib A. Fahmy Arvind Easwaran

Cyber Physical Systems (CPSs), such as those found in modern vehicles, include a number of important time and safety-critical functions. Traditionally, applications are mapped to several dedicated electronic control units (ECUs), and hence, as new functions are added, compute weight and cost increase considerably.%ECU consolidation, where multiple functions are combined on fewer ECUs is an important area, but traditional software ECUs fail to offer the required performance, parallelism, and isolation to support this. With increasing computational and communication demands, traditional software ECUs fail to offer the required performance to provide determinism and predictability, while multi-core approaches fail to provide sufficient isolation between tasks. Hybrid FPGAs, combining a processor and reconfigurable fabric on a single die, allow for parallel hardware implementation of complex sensor processing tightly coupled with the flexibility of software on a processor. We demonstrate the advantages of such architectures in consolidating distributed processing with predictability, determinism and isolation, enabling ECU consolidation and bandwidth reduction.

Predictability

Cyber-physical system

Multi-core processor

10.1109/cpsna.2014.14

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Citations (20)

Experiments in Mapping Expressions to DSP Blocks

Field-Programmable Custom Computing Machines (2014)

Bajaj Ronak Suhaib A. Fahmy

Mapping complex mathematical expressions to DSP blocks by relying on synthesis from pipelined code is inefficient and results in significantly reduced throughput. We have developed a tool to demonstrate the benefit of considering the structure and pipeline arrangement of the DSP block in mapping of functions. Implementations where the structure of the DSP block is considered during pipelining achieve double the throughput of other methods, demonstrating that the structure of the DSP block must be considered when scheduling complex expressions.

Implementation

Software pipelining

Source

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High Throughput 2D Spatial Image Filters on FPGAs

arXiv (Cornell University) (2017)

Abdullah Al-Dujaili Suhaib A. Fahmy

FPGAs are well established in the signal processing domain, where their fine-grained programmable nature allows the inherent parallelism in these applications to be exploited for enhanced performance. As architectures have evolved, FPGA vendors have added more heterogeneous resources to allow often-used functions to be implemented with higher performance, at lower power and using less area. DSP blocks, for example, have evolved from basic multipliers to support the multiply-accumulate operations that are the core of many signal processing tasks. While more features were added to DSP blocks, their structure and connectivity has been optimised primarily for one-dimensional signal processing. Basic operations in image processing are similar, but performed in a two-dimensional structure, and hence, many of the optimisations in newer DSP blocks are not exploited when mapping image processing algorithms to them. We present a detailed study of two-dimensional spatial filter implementation on FPGAs, showing how to maximise performance through exploitation of DSP block capabilities, while also presenting a lean border pixel management policy.

Spatial filter

10.48550/arxiv.1710.05154

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Smart Network Interfaces for Advanced Automotive Applications

IEEE Micro (2018)

Shanker Shreejith Suhaib A. Fahmy

The computing integrated in modern vehicles has increased dramatically over the last decade, with many cars having over 50 compute units controlling critical and non-critical functions.These ECUs communicate over increasingly complex and heterogeneous networks, and these systems combined present challenges in terms of scalability, validation, and security.In this article, we present the concept of smart network interfaces that incorporate programmable computation in the datapath to enable more features at the network layer, thereby offloading auxiliary tasks from the ECU processor.System-level capabilities such as hardware-level fault tolerance, application consolidation with sufficient isolation, and system-level security at each compute node become possible without disturbing the core computational functions of the ECUs.We demonstrate this approach with practical prototyping in FPGAs.

Networking hardware

10.1109/mm.2018.022071137

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Adapting the DySER Architecture with DSP Blocks as an Overlay for the Xilinx Zynq

ACM SIGARCH Computer Architecture News (2016)

Abhishek Kumar Jain Xiangwei Li Suhaib A. Fahmy Douglas L. Maskell

Coarse-grained overlay architectures have been shown to be effective when paired with general purpose processors, offering software-like programmability, fast compilation, and improved design productivity. These architectures enable general purpose hardware accelerators, allowing hardware design at a higher level of abstraction, but at the cost of area and performance overheads. This paper examines the DySER overlay architecture as a hardware accelerator paired with a general purpose processor in a hybrid FPGA such as the Xilinx Zynq. We evaluate the DySER architecture mapped on the Xilinx Zynq and show that it suffers from a significant area and performance overhead. We then propose an improved functional unit architecture using the flexibility of the DSP48E1 primitive which results in a 2.5 times frequency improvement and 25% area reduction compared to the original functional unit architecture. We demonstrate that this improvement results in the routing architecture becoming the bottleneck in performance.

10.1145/2927964.2927970

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A model for distributed in-network and near-edge computing with heterogeneous hardware

Future Generation Computer Systems (2019)

Ryan A. Cooke Suhaib A. Fahmy

Implementation

Data Processing

Edge device

Distributed design patterns

Symmetric multiprocessor system

10.1016/j.future.2019.11.040

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Citations (22)

Initiation Interval Aware Resource Sharing for FPGA DSP Blocks

Bajaj Ronak Suhaib A. Fahmy

Resource sharing attempts to minimise usage of hardware blocks by mapping multiple operations onto same block at the cost of an increase in schedule length and initiation interval (II). Sharing multi-cycle high-throughput DSP blocks using traditional approaches results in significantly high II, determined by structure of dataflow graph of the design, thus limiting achievable throughput. We have developed a resource sharing technique that minimises the number of DSP blocks and schedule length given an II constraint.

Shared resource

Limiting

10.1109/fccm.2016.40

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Lightweight Authentication for Secure Automotive Networks

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 (2015)

Philipp Mundhenk Sebastian Steinhorst Martin Lukasiewycz Suhaib A. Fahmy Samarjit Chakraborty

We propose a framework to bridge the gap between secure authentication in automotive networks and on the internet. Our proposed framework allows runtime key exchanges with minimal overhead for resource-constrained in-vehicle networks. It combines symmetric and asymmetric cryptography to establish secure communication and enable secure updates of keys and software throughout the lifetime of the vehicle. For this purpose, we tailor authentication protocols for devices and authorization protocols for streams to the automotive domain. As a result, our framework natively supports multicast and broadcast communication. We show that our lightweight framework is able to initiate secure message streams fast enough to meet the real-time requirements of automotive networks.

Secure Communication

10.7873/date.2015.0174

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Citations (36)

A high speed open source controller for FPGA Partial Reconfiguration

Kizheppatt Vipin Suhaib A. Fahmy

Partial Reconfiguration (PR) is an advanced technique, which improves the flexibility of FPGAs by allowing portions of a design to be reconfigured at runtime by overwriting parts of the configuration memory. PR is an important enabler for implementing adaptive systems. However, the design of such systems can be challenging, and this is especially true of the configuration controller. The generally supported methods and IP have low throughput, resulting in long configuration time that precludes PR from systems where this operation needs to be fast. In this paper, we present a high-speed configuration controller that provides several features useful in adaptive systems. The design has been released for use by the wider research community.

Control reconfiguration

Enabling

10.1109/fpt.2012.6412113

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Citations (55)