Kazunori Kuribara

National Institute of Advanced Industrial Science and Technology

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Takashi Satō

Kyoto University

Tsuyoshi Sekitani

Osaka University

Tomoyuki Yokota

The University of Tokyo

Takao Someya

The University of Tokyo

Manabu Yoshida

National Institute of Advanced Industrial Science and Technology

Ute Zschieschang

Max Planck Institute for Solid State Research

Hagen Klauk

Max Planck Institute for Solid State Research

Sei Uemura

National Institute of Advanced Industrial Science and Technology

Yasuhiro Ogasahara

National Institute of Advanced Industrial Science and Technology

Kazuo Takimiya

RIKEN Center for Emergent Matter Science

Cooperative Institutions

The University of Tokyo

National Institute of Advanced Industrial Science and Technology

Osaka University

Tokyo Institute of Technology

Tokyo University of Science

Japan Science and Technology Agency

Kyoto University

Tokyo University of Information Sciences

University of Tsukuba

Tohoku University

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Thermal stability of solution processable n-type organic semiconductor

The Japan Society of Applied Physics (2018)

Kazunori Kuribara Taiki Nobeshima Atsushi Takei Takehito Kozasa Sei Uemura

Thermal Stability

Organic semiconductor

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Spatial control of the threshold voltage of low-voltage organic transistors by microcontact printing of alkyl- and f luoroalkyl-phosphonic acids

MRS Communications (2011)

Ikue Hirata Ute Zschieschang Frederik Ante Tomoyuki Yokota Kazunori Kuribara

Microcontact Printing

Stamping

10.1557/mrc.2011.11

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Citations (7)

Low operational organic integrated circuits using self-assembled monolayers

IEICE Technical Report; IEICE Tech. Rep. (2010)

Kenjiro Fukuda Kazunori Kuribara Tsuyoshi Sekitani Ute Zschieschang Hagen Klauk

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Recovery-aware bias-stress degradation model for organic thin-film transistors considering drain and gate bias voltages

Japanese Journal of Applied Physics (2019)

K. Oshima Michihiro Shintani Kazunori Kuribara Yasuhiro Ogasahara Takashi Satō

Due to the limited lifetime of organic thin-film transistors (OTFTs), it is crucial to predict the degradation of circuit performance at the early stage of design. In this paper, we discuss bias stress voltage degradation of OTFTs. Through the measurements, we show that the gate voltage affects more significantly in the short term device degradation than drain current flow and that the degradation recovers partially when the given bias voltage is removed. We also propose a novel bias stress voltage degradation model that can express the model-parameter degradation and its recovery. The proposed model can fit the temporal shift of the measured model parameters very well.

Degradation

Biasing

Gate voltage

10.7567/1347-4065/ab6460

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Citations (7)

Separation of bias stress degradation between insulator and semiconductor carrier trapping in organic thin-film transistors

Japanese Journal of Applied Physics (2021)

K. Oshima Song Bian Kazunori Kuribara Takashi Satō

Abstract Organic thin-film transistors (OTFTs) are studied intensively for realizing practical applications of flexible or large-area circuits, but rapid degradation of OTFTs due to stress voltage or reaction with water vapor or oxygen in the air limits their lifetime. In order to analyze the cause of rapid bias-stress degradation, we propose a method that separates the cause of threshold voltage ( V th ) shift into insulator carrier trapping (ICT) and semiconductor carrier trapping components. The experimental results show that the ICT components account for nearly 50% of the total V th shift in n-type OTFTs, while the ICT-induced V th shifts is about 20% of the total V th shift in p-type OTFTs regardless of the insulator materials: SAM or parylene. The experimental results suggest that the short lifetime of the n-type OTFTs with SAM-based insulator is caused by the instability of the SAM-based insulator due to ICT. In addition, the instability of the p-type OTFTs with SAM-based insulator is discussed based on measurement, and as a result, capacitance shift due to ICT may also affect the degradation of highly biased p-type OTFTs.

10.35848/1347-4065/abdcb2

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Citations (2)

Atmospheric-pressure plasma oxidation of aluminum for large-area electronics

Journal of Applied Physics (2019)

Kazunori Kuribara Taiki Nobeshima Takehito Kodzasa Sei Uemura Manabu Yoshida

We developed an atmospheric pressure plasma (APP) process for forming metal oxides and self-assembled monolayers (SAMs) without a vacuum process. SAMs are frequently utilized for surface modification. In particular, a combination of aluminum oxide (AlOx) and alkylphosphonic acid is used as the gate dielectric in flexible electronics, with a low operating voltage of 2 V because of its simple fabrication process at room temperature in air. However, when using a combination of SAMs and AlOx as the gate dielectric, it is necessary to form a metal oxide with sufficient thickness using a vacuum plasma process to reduce the leakage current, which is not suitable for use in flexible large-area electronics. In this study, we resolved this problem by utilizing an APP process and substrate heating instead of the vacuum plasma process. Heating a substrate above 100 °C forms a sufficient AlOx layer. The leakage current of plasma-processed AlOx with SAMs was reduced by three orders of magnitude compared to that of natural AlOx with SAMs. X-ray photoelectron spectroscopy revealed a time dependence of the thickness of AlOx. An exposure time of 100 s was sufficient to form an AlOx layer with a thickness of 4 nm. An organic transistor with this APP treatment of AlOx and SAMs showed a mobility of 1.4 cm2/V s and an on/off ratio of 104 within 2 V. We also fabricated an inverter and a ring oscillator circuit with an inverter gain of more than 300 and an oscillation frequency of 40 Hz.

Leakage (economics)

10.1063/1.5109203

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Citations (8)

3V-Operation Organic Transistors on Shape-Memory Film with Polyimide Planarization Layer

Extended Abstracts of the 2020 International Conference on Solid State Devices and Materials (2011)

Yasuhiro Kato Tsuyoshi Sekitani Tomoyuki Yokota Kazunori Kuribara Ute Zschieschang

Chemical Mechanical Planarization

10.7567/ssdm.2011.b-8-6

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Mechanically and electrically robust metal-mask design for organic CMOS circuits

Japanese Journal of Applied Physics (2018)

Michihiro Shintani Zhaoxing Qin Kazunori Kuribara Yasuhiro Ogasahara Masayuki Hiromoto

The design of metal masks for fabricating organic CMOS circuits requires the consideration of not only the electrical property of the circuits, but also the mechanical strength of the masks. In this paper, we propose a new design flow for metal masks that realizes coanalysis of the mechanical and electrical properties and enables design exploration considering the trade-off between the two properties. As a case study, we apply a "stitching technique" to the mask design of a ring oscillator and explore the best design. With this technique, mask patterns are divided into separate parts using multiple mask layers to improve the mechanical strength at the cost of high resistance of the vias. By a numerical experiment, the design trade-off of the stitching technique is quantitatively analyzed, and it is demonstrated that the proposed flow is useful for the exploration of the designs of metal masks.

Image stitching

Ring oscillator

10.7567/jjap.57.04fl05

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Citations (6)

Electric and structural characterizations on annealed dinaphthothienothiophene thin-film transistors.

Extended Abstracts of the 2020 International Conference on Solid State Devices and Materials (2011)

Kazunori Kuribara H. Wang Naoya Uchiyama Kenjiro Fukuda Tomoyuki Yokota

10.7567/ssdm.2011.b-6-6

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Low Operation Voltage Organic Transistors on Shape-Memory Film with Planarization