Abstract European states may no longer expect inter‐state violence, but they do expect complex threats emanating from storms, epidemics, terror attacks and earthquakes. The EU has answered these threats through the rapid and far‐reaching institutionalization of European security cooperation. However, member states hesitate to use their common capacities. While both intergovernmental and constructivist approaches treat this pattern as evidence of weak integration and as unimportant to the European security community, we examine this cooperation through the lens of practice theory and reveal how the growth of EU capacities is fully compatible with a critical and cautious approach to activating these resources in the everyday work of national officials. Using unique empirical data retrieved through participant observation in the first multisectoral crisis management exercise held by the EU, the findings of this analysis sketch the contours of a new type of security community.
Capitalising on the high-speed switching capability of 650 V GaN FETs in power-electronic bridge-legs is challenging. Whilst active gate driving has previously been shown to help overcome adverse switching behaviour, the best results are likely to be achieved through a combination of uncompromised circuit layout and active gate driving. A fully integrated dual-channel driver would minimise external circuitry and allow power devices to be placed as close together as possible. This would facilitate simultaneous minimization of parasitic inductances in the gate-drive and power-circuit loops. Other benefits would include ease of use, lower BOM cost, and providing a step towards full integration of driver and power stage. This paper presents three circuit blocks vital to the implementation of a fully integrated dual-channel gate driver - A 100 ps resolution, digitally-controlled active gate driver IC, a sub-ns propagation delay level shifter with 200 V/ns slew-rate immunity, and a regulated bootstrap supply that maintains its output voltage regardless of any switch-node undershoot during switching events. Measurement results show the efficacy of the high-resolution active gate driver in a GaN bridge leg, and the sub-ns propagation delay of the level shifter, both fabricated in a 50 V CMOS process. Simulation results demonstrate the slew-immunity of the level shifter, and operation of the bootstrap supply. It is also inferred how to increase the voltage rating of the level-shifter and bootstrap without adversely affecting performance.
Abstract In 2021 JET exploited its unique capabilities to operate with T and D–T fuel with an ITER-like Be/W wall (JET-ILW). This second major JET D–T campaign (DTE2), after DTE1 in 1997, represented the culmination of a series of JET enhancements—new fusion diagnostics, new T injection capabilities, refurbishment of the T plant, increased auxiliary heating, in-vessel calibration of 14 MeV neutron yield monitors—as well as significant advances in plasma theory and modelling in the fusion community. DTE2 was complemented by a sequence of isotope physics campaigns encompassing operation in pure tritium at high T-NBI power. Carefully conducted for safe operation with tritium, the new T and D–T experiments used 1 kg of T (vs 100 g in DTE1), yielding the most fusion reactor relevant D–T plasmas to date and expanding our understanding of isotopes and D–T mixture physics. Furthermore, since the JET T and DTE2 campaigns occurred almost 25 years after the last major D–T tokamak experiment, it was also a strategic goal of the European fusion programme to refresh operational experience of a nuclear tokamak to prepare staff for ITER operation. The key physics results of the JET T and DTE2 experiments, carried out within the EUROfusion JET1 work package, are reported in this paper. Progress in the technological exploitation of JET D–T operations, development and validation of nuclear codes, neutronic tools and techniques for ITER operations carried out by EUROfusion (started within the Horizon 2020 Framework Programme and continuing under the Horizon Europe FP) are reported in (Litaudon et al Nucl. Fusion accepted), while JET experience on T and D–T operations is presented in (King et al Nucl. Fusion submitted).
The alignment of code in the flash memory of deeply embedded SoCs can have a large impact on the total energy consumption of a computation. We investigate the effect of code alignment in six SoCs and find that a large proportion of this energy (up to 15% of total SoC energy consumption) can be saved by changes to the alignment. A flexible model is created to predict the read-access energy consumption of flash memory on deeply embedded SoCs, where code is executed in place. This model uses the instruction level memory accesses performed by the processor to calculate the flash energy consumption of a sequence of instructions. We derive the model parameters for five SoCs and validate them. The error is as low as 5%, with a 11% average normalized RMS deviation overall. The scope for using this model to optimize code alignment is explored across a range of benchmarks and SoCs. Analysis shows that over 30% of loops can be better aligned. This can significantly reduce energy while increasing code size by less than 4%. We conclude that this effect has potential as an effective optimization, saving significant energy in deeply embedded SoCs.
We introduce nOS, a "nano-sized" fully distributed operating system aimed at large-scale, many-core embedded systems. nOS enables dynamic runtime optimisation of energy and execution time through lightweight and scalable distributed protocols. nOS implements new dynamic resource optimisation algorithms, and provides an intuitive and easy-to-use programmer API that supports runtime task energy optimisation through dynamic frequency scaling, transparent task communication tracking, and automatic task mapping. Critically, nOS has a completely distributed implementation, providing excellent scalability. Contrary to other approaches, the dynamic runtime optimisations require no a priori knowledge of workload or communication patterns. By generating runtime measurements of thread performance, core load, and process communication, we show that nOS can deliver improvements that would not be possible with only static analysis. Using a many-core system called Swallow, we show a <;3kB fullstack implementation of nOS together with application, OS and hardware. Using two applications with different communication patterns, we illustrate the power and flexibility of our approach, as well as various tradeoffs in energy and performance from making better mapping choices than would be available offline.
Deeply embedded systems often have the tightest constraints on energy consumption, requiring that they consume tiny amounts of current and run on batteries for years. However, they typically execute code directly from flash, instead of the more energy efficient RAM. We implement a novel compiler optimization 1 that exploits the relative efficiency of RAM by statically moving carefully selected basic blocks from flash to RAM. Our technique uses integer linear programming, with an energy cost model to select a good set of basic blocks to place into RAM, without impacting stack or data storage. We evaluate our optimization on a common ARM microcontroller and succeed in reducing the average power consumption by up to 41% and reducing energy consumption by up to 22%, while increasing execution time. A case study is presented, where an application executes code then sleeps for a period of time. For this example we show that our optimization could allow the application to run on battery for up to 32% longer. We also show that for this scenario the total application energy can be reduced, even if the optimization increases the execution time of the code.
The Skip-link architecture dynamically reconfigures Network-on-Chip (NoC) topologies in order to reduce the overall switching activity in many-core systems. The proposed architecture allows the creation of long-range Skip-links at runtime to reduce the logical distance between frequently communicating nodes. This offers a number of advantages over existing methods of creating optimised topologies already present in research, such as the Reconfigurable NoC (ReNoC) architecture and static Long-Range Link (LRL) insertion. This architecture monitors traffic behaviour and optimises the mesh topology without prior analysis of communications behaviour, and is thus applicable to all applications. The technique described here does not utilise a master node, and each router acts independently. The architecture is thus scalable to future many-core networks. The authors evaluate the performance using a cycle-accurate simulator with synthetic traffic patterns and compare the results to a mesh architecture, demonstrating logical hop count reductions of 12-17%. Coupled with this, up to a doubling in critical load is observed, and the potential for 10% energy reductions on a 16×16 node network.
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