Lanthanum silicate gate dielectric MIS devices have been studied in relation to material stability and device reliability. Uncapped dielectric films 2 nm thick exposed to air for 7 months show very little increase in hydroxide formation (~2%, determined by XPS) if experiencing an initial high temperature anneal (1000{degree sign}C, 10 sec). Likewise, after an initial 1000{degree sign}C anneal, MIS device characteristics show no appreciable change over this time period. Negative bias temperature instability measurements on MIS devices at 100{degree sign}C and -2.5 V reveal process-temperature-dependent midgap voltage shifts, with negative shifts (>50 mV) observed for <=900{degree sign}C processing indicating predominantly hole trapping, and small (10 mV) positive shifts for samples experiencing a 1000{degree sign}C process temperature, well within accepted device reliability limits. These results indicate that lanthanum silicate will not introduce significant device lifetime issues when optimally processed.
The effective work functions (EWF) of thin transparent conducting oxide (TCO) interlayers, i.e. indium tin oxide (ITO) and indium zinc tin oxide (IZTO), on lanthanum silicate metal-insulator-semiconductor (MIS) devices were examined. The properties were compared to those obtained using conventional metal electrodes. It was found that the EWF of all metal gates investigated was lowered by ~0.3 - 0.4 compared to expected values, due to effects related to the lanthanum silicate dielectric stack. The presence of the TCO electrode layer yielded EWF values ranging from 4.05 to 4.45 eV depending primarily on the annealing condition, regardless of the TCO type. As it is known that ITO can have a work function ~4.75 eV, the presence of the oxide electrode still results in an EWF ~0.3 - 0.4 eV below expected values. These results indicate that EWF lowering in lanthanum silicate gate stacks is not strongly dependent on the top interface.
With the steep expansion of the n-type 4H-SiC power metal-oxide-semiconductor field-effect transistor (MOSFET) market space, gate oxide reliability is gaining more and more attention. Although there exist several reports dealing with the bias temperature instability (BTI) under both positive and negative gate biases, gate oxide lifetime evaluations predominantly focus on positive gate bias time-dependent dielectric breakdown (TDDB) stresses for n-channel SiC MOSFETs. In this work we address that gap. From the negative gate bias TDDB data measured at 175 °C and at a gate oxide electric field of about 4 MV/cm, an intrinsic lifetime of 1E8 hours has been predicted, which closely matches with the results obtained from similar devices under positive gate stress. Also, in this work the correlation between failure location in a MOSFET unit cell and the failure signatures during TDDB stress have been established, and an explanation from a device physics standpoint has been provided. The identification of the failure location in the unit cell from in-situ gate leakage data without the need of physical failure analysis can turn out to be key during the early phase of a new process development activity.
In this work, we utilize electrically detected magnetic resonance via the bipolar amplification effect to explore the physical and chemical nature of defects at the 4H-SiC/SiO 2 interface in metal-oxide-semiconductor field effect transistors. Defects at and very near the 4H-SiC/SiO 2 interface are involved in bias temperature instabilities in 4H-SiC transistor technology. Of particular relevance to reliability physics, our results indicate that oxygen deficient silicon atoms in the near-interface oxide, known as E' centers, can be greatly reduced utilizing nitric oxide and barium annealing. E' centers have been directly linked to bias temperature instabilities in 4H-SiC technology.
Abstract Pb(ZrxTi1−x)O3 (PZT) based ferroelectric capacitors have been produced at 600°C on R-cut sapphire and Si-doped (100) GaAs substrates using a pulsed laser ablation deposition (PLAD) technique. La0.5Sr0.5CoO3 (LSCO) conducting electrodes deposited using PLAD serve as top and bottom electrodes. X-ray diffraction results show that the PZT film is polycrystalline and phase-pure in both cases. Electrical characterization of the films show remanant polarization in excess of 20 μC/cm2. Results of long term properties show that these capacitors: are very tolerant to extremely large numbers of switching cycles; retain charges over very long periods of time; and do not show a strong tendency for their dipoles to be imprinted in a preferred direction.
We report a thermally stable N-metal process in which surface passivation of HfSiO dielectric using thin layers of La 2 O 3 , deposited by either MBE or PVD, significantly shifts the metal gate effective work function toward the Si conduction band edge. Well-behaved transistors with L g down to 70 nm have been fabricated with threshold voltage of 0.25V, mobility up to 92% of the universal SiO 2 mobility, and T inv ~1.6 nm
Ion-induced leakage current degradation, and single-event burnout may be manifestestations of the same device mechanisms in both silicon carbide power diodes and MOSFETs. In all cases there is a migration of the electrical field from the front body-drain interface to the back epi-drain n+ interface, with a peak exceeding the critical electric field of silicon carbide, causing avalanche generation which enables high short-duration power densities during an approximate 20 psec window after the ion strike. The degradation effect in JBS SiC diodes seems to be independent of the length of the epitaxial region for different voltage-rated diodes.
High performance 15 kV n-GTOs were demonstrated for the first time in 4H-SiC. The device utilized a 140 μm thick, lightly doped n-type drift layer, with 1450°C lifetime enhancement oxidation, which resulted in a carrier lifetime of 17.5 μs. The p + backside injector layer was thinned to minimize parasitic resistances. A room temperature forward voltage drop of 5.18 V was observed at a current density of 100A/cm 2 . A 1 cm 2 device showed a leakage current of 0.17 μA at 15 kV. The 4H-SiC n-GTO showed latching characteristics, and showed a turn-off time of 170 ns in a resistive load switching setup, which represents about a factor of 45 improvement in turn-off speed over 4H-SiC p-GTOs with comparable voltage and current ratings.
Bulk mobility and dopant activation of implanted species into 4H-SiC plays a crucial role in the carrier conduction, blocking behavior, and channel properties of a 4H-SiC vertical power MOSFET. Nitrogen and phosphorus ion implantation became the norm as n-type dopants for 4H-SiC. Therefore, the doping and temperature behavior of both species in 4H-SiC needs to be well characterized. In this study, we report a comparison in electrical characteristics between nitrogen and phosphorus implanted 4H-SiC as a function of temperature for various doping levels. For this purpose, 4-point van der Pauw samples are prepared, resistivity and Hall measurements are conducted. We found that resistivities drop as temperature increases from 140 K with phosphorus having higher resistivities at all implanted doping concentrations. The carrier concentrations increase with increase of temperature, indicating incomplete ionization of dopants. Mobilities drop at low temperature due to increased impurity scattering, reaches a peak near 300 K and drops at higher temperature due to increased phonon scattering. From the obtained data, using a two-level charge neutrality equation, the activation percentage and ionization energies of dopants in hexagonal and cubic sites for both species are extracted and compared.
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