Summarizes results of a project which was conducted over the last 3 years at the University of Saarbrucken. Goal of the project was to construct a fault tolerant parallel machine for scientific applications and for running APL programs. The machine is supposed to tolerate failures of single slave processors, single disks and single routing chips in the interconnection network. After failure the machine reconfigures itself and continues work at the original speed.< >
Synchronization is inherent to parallel computing and comprises many aspects. One aspect is the access control to shared data, especially important in MIMD shared-memory architectures. Several locking mechanisms have been proposed to perform this task. Most of these schemes rely on very little hardware support, such as atomic read-modify-write operations. Today, the amount of hardware required to implement a locking mechanism is not a major constraint and will be even less important in the future. This makes it interesting to investigate schemes with more flexibility, better performance, and improved ease of use, that rely more on hardware assisted circuits than previous suggestions. In this paper multi-dimensional locking schemes that allocate locks on-line are presented. A lock is assigned to the access control of a data structure only during the time this structure needs to be locked. Three specific schemes are proposed. Two offer the possibility of locking sub-structures within multi-dimensional arrays. All three schemes protect locked structures against accesses of misbehaving threads.
We sketch the physical design of a prototype of a PRAM architecture based on Ranade's Fluent Machine. We describe a specially developed processor chip with several instruction streams and a fast butterfly connection network. For the realization of the network we consider alternatively optoelectronic and electric transmission. We also discuss some basic software issues.
