A novel complementary metal–oxide–semiconductor (CMOS) process compatible and self-aligned fabrication method for the dual-gate single-electron transistor (DG-SET) is presented. The performance of previous versions of the DG-SET was limited by inherent parasitic elements and its fabrication process was divergent from conventional CMOS, limiting the possibility of co-integration. Through simulation, the parasitic elements are confirmed to be caused by the non-self-alignment of the control gate, side gates, and source/drain. To resolve such issues, a new type of DG-SET was fabricated using a self-aligned process. Measurement results obtained at room temperature revealed clear Coulomb oscillation peaks in the trans-conductance curve. Through parameter extraction and its comparison with previous results, this is confirmed to be the consequence of single-electron tunneling. Also, in order to confirm that the single-electron tunneling is caused by the electrically induced tunneling barriers, and not by random fluctuations along the SOI active, low temperature measurement results for devices with different parameters is compared.
We demonstrate gate-tunable resonant tunneling and negative differential resistance in the interlayer current–voltage characteristics of rotationally aligned double bilayer graphene heterostructures separated by hexagonal boron nitride (hBN) dielectric. An analysis of the heterostructure band alignment using individual layer densities, along with experimentally determined layer chemical potentials indicates that the resonance occurs when the energy bands of the two bilayer graphene are aligned. We discuss the tunneling resistance dependence on the interlayer hBN thickness, as well as the resonance width dependence on mobility and rotational alignment.
Recent advances in the fabrication of two dimensional heterostructures have facilitated the study of resonant tunneling based interlayer tunnel FETs (ITFETs) which offer the possibility of sharp negative differential resistance (NDR) characteristics [1-3]. More recently, a new technique whereby rotational alignment of the two conduction layers can be guaranteed has been developed [4]. Using a similar technique, we have exhaustively explored various combinations of graphene conduction layers with differing layer thickness. Due to the varying band structures with graphene layer thickness, we observe interesting points that could serve as a basis for obtaining ITFETs with improved performance; i.e. higher peak-to-valley current ratio (PVCR) of the NDR.
As the limits of CMOS performance are approached, industry, government and academia alike search for so-called beyond “CMOS devices” to replace CMOS either globally or, more likely initially, for specific applications. This discussion focuses on our ongoing efforts to develop and apply one such device concept, resonant interlayer tunnel field effect transistor (ITFETs), addressing essential physics, device design and fabrication, and circuit applications. As considered here, resonant ITFETs employ stacks of two-dimensional van der Waals materials to form both parallel conduction channels and intervening dielectric tunnel barriers. Due to the requirement for surface-parallel crystal momentum conservation between the layers, resonant tunneling between such two dimensional layers is not nominally subject to thermal smearing of the resonance over a few k B T as in more conventional resonant tunneling systems. Thus, such interlayer resonant tunneling potentially could be used for low voltage room temperature applications, with nano-scale devices operating at a tenth of a volt or less in principle. In addition, this layered 2D geometry readily lends itself to electrostatic gating of the interlayer tunneling, from above and even below. The concept of such interlayer resonant tunneling has been around for years. However, the use of 2D van der Waals materials such as monolayer or Bernal-stacked bilayer graphene as channel materials, hexagonal boron-nitride (hBN) as dielectrics, and/or various transition metal dichalcogenides such as MoS 2 or ReS 2 as channel or dielectric materials, in various combinations also lends itself to atomically precise control of layer thicknesses and interfaces, avoiding, e.g., inhomogeneous resonance broadening. However, there are many challenges to achieving such resonant ITFETs and using them in circuit applications. For example, rotational alignment between layers is essential to interface-parallel crystal-momentum conserving resonant tunneling for van der Waals channel materials with peripheral band edge energy valleys, which is the norm. At least in experimental device fabricated via layer exfoliation, crystallographic alignment between the channel layers had been challenging to achieve. However, among the authors, we recently achieved a breakthrough in this respect allowing very precise control over rotational alignment. Alternatively, the use of the direct gap channel material such as ReS 2 should substantially remove this concern with respect to resonant broadening. However, we also demonstrate using density functional theory that rotational misalignment of the tunnel dielectric with the channel material can greatly reduce the overall amplitude of the interlayer tunneling current by, specifically, reducing the coupling across the channel-to-dielectric interfaces (vs. by band structure misalignment) even with rotational alignment between the channel layers. Toward eventual nanoscale devices, we show that Heisenberg position-momentum uncertainty translated to energy uncertainty via the carrier group velocity, dE/d( ħk) , will lead to resonance broadening, and the more so for fast carrier. Another concern is intrinsic spectral broadening of the crystal momentum states by scattering. Nevertheless, if fabrication issues could be overcome, we show that low-voltage operation of nanoscale devices should be possible. However, the negative differential resistance (NDR)-current-voltage (I-V) characteristics of these devices make use in conventional circuits challenging. The use of clocked power supplies allows basic logic gates such as inverters, buffers, and NAND and NOR gates to be created. It also results in each gate effectively being a latch, but also effectively having an activity factor of unity for each clock cycle, which requires new approaches to higher level circuit design. We show that for certain applications such as ultra-deep pipelining and ultra-compact circuits, and perhaps non-conventional computing schemes, resonant ITFET circuits could provide advantages over CMOS. (This work is supported by the Nanoelectronics Research Initiative (NRI) through the Southwest Academy of Nanotechnology (SWAN)).
A Recessed-Channel Dual-Gate Single Electron Transistor (RCDG-SET) which has the possibility of room temperature operation is proposed. Side gates of a RCDG-SET form electrical tunneling barriers around a recessed channel, which is newly introduced. Not only gate but also a recessed channel is self aligned to source and drain. Characteristics of a RCDG-SET are compared with those of previous DG-SETs through device simulation (SILVACO). Due to a recessed channel and a self aligned structure, MOSFET current which causes low Peak-to-Valley Current Ratio (PVCR) is suppressed. This property of a RCDG-SET is expected to contribute for room temperature operation.
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