Yuan‐Ho Chen

Chang Gung University

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Co-Authors

Tsin‐Yuan Chang

National Tsing Hua University

Chih‐Wen Lu

National Yang Ming Chiao Tung University

Shinn‐Yn Lin

Chang Gung Memorial Hospital

Szi-Wen Chen

Chang Gung University

Chung‐Yi Li

Chang Gung University

Ming‐Lang Tseng

Asia University

Rou‐Shayn Chen

Chang Gung Memorial Hospital

Hsin-Tung Hua

Chang Gung University

Chieh‐Yang Liu

Chang Gung University

Yun-Hua Tseng

Chang Gung University

Cooperative Institutions

Chang Gung University

National Tsing Hua University

National Taiwan University

National Yang Ming Chiao Tung University

National Cheng Kung University

Chang Gung Memorial Hospital

Chung Yuan Christian University

Lunghwa University of Science and Technology

Institute of Nuclear Energy Research

Atomic Energy Council

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Improvement of control-law derivation for D-Σ digital controlled three-phase four-wire inverter

2022 IEEE Applied Power Electronics Conference and Exposition (APEC) (2015)

T.-F. Wu L.-C. Lin Po‐Chiao Lin Yuan‐Ho Chen Y.-R. Chang

A division-summation (D-Σ) digital control can track sinusoidal reference current in four operation modes: grid-connection, rectification, PF leading and PF lagging mode. It can overcome the limitation of abc to α-β-γ frame transformation and cover wide filter inductance variation. However, the switching sequences for the four modes are different from each other, increasing complexity of firmware programming. In this paper, improvement of control-law derivation for D-Σ digital controlled three-phase four-wire inverter is presented. By selecting the zero crossing points of phase voltages as region transitions, the control laws and the related parameter tables for the four modes can be unified to a general form. The three-phase four-wire inverter topology can be also adopted as an uninterruptible power supply (UPS) application and it can supply unbalanced, linear and rectified loads. With the proposed load impendence estimation, the D-Σ digital control laws can be applied for voltage tracking. The switching sequences of the four modes and UPS mode are all unified to the switching pattern of the grid-connection mode. Additionally, a D-Σ transformation matrix is identified to simplify the derivation procedure of the division (D) and summation (Σ), which can obtain the control law directly. Experimental results measured from a 10 kVA inverter have verified the analysis and discussion.

Uninterruptible power supply

Three-phase

Digital Control

10.1109/apec.2015.7104549

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An Automated Toolchain for QUBO-based Optimization with Quantum-inspired Annealers

2022 19th International SoC Design Conference (ISOCC) (2023)

Yunting Zhang Chin-Fu Nien Chia-Wei Lin Wen-Jui Chao Chen-Yu Liu

Recently, quantum computers have drawn attention to their potential to solve problems faster than classical computers. However, quantum hardware's limited practicality and scalability have led to an interest in alternative approaches to solving optimization problems. One such approach is classical quantum-inspired annealers, which provide efficient and scalable solutions for combinatorial optimization problems (COPs) using classical hardware. To use annealers, COPs must be formulated as quadratic unconstrained binary optimization (QUBO) forms. Current tools require coding expertise and manual parameter tuning, posing barriers to entry. To address these challenges, we developed a user-friendly software toolchain that offers several advantages. Our toolchain features a friendly input and output interface, an automated parameter tuner, and a library of commonly encountered COPs. Our software toolchain's accessibility promotes the use of quantum-inspired annealers and accelerates the development of practical solutions for real-world problems.

Toolchain

10.1109/isocc59558.2023.10396459

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Notice of Removal A high resolution FPGA-based TDC with nonlinearity calibration

Yuan‐Ho Chen Chih‐Wen Lu Tsin‐Yuan Chang Chin Hsia

This paper proposes multi-path delay line (MPDL) time-to-digital converter (TDC). Instead of traditional tapped delay line (TDL) TDC, the proposed MPDL-TDC can improve the linearity performance effectively. Implemented in a Xilinx XC5VLX110T-1FF1136 field-programmable gate array (FPGA) device, the proposed MPDL-TDC has 60 ps time resolution, and the ranges of differential non-linearity (DNL) and integral non-linearity (INL) are [-0.52,0.52] and [-0.79,1.06] least-significant-bit (LSB), respectively. Furthermore, 37.25 ps root-mean-square (RMS) is measured for the proposed MPDL-TDC inputting a constant delay source. Therefore, the proposed MPDL-TDC is recommended to implement in FPGA-based TDC achieving a high-resolution time and linearity performance.

Linearity

Differential nonlinearity

Integral nonlinearity

Time-to-Digital Converter

10.1109/msna.2012.6324513

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Citations (6)

A low-area high-efficiency video coding inverse transform core using resource and time sharing architecture

EURASIP Journal on Advances in Signal Processing (2020)

Yuan‐Ho Chen Chieh‐Yang Liu

Abstract In this paper, a very-large-scale integration (VLSI) design that can support high-efficiency video coding inverse discrete cosine transform (IDCT) for multiple transform sizes is proposed. The proposed two-dimensional (2-D) IDCT is implemented at a low area by using a single one-dimensional (1-D) IDCT core with a transpose memory. The proposed 1-D IDCT core decomposes a 32-point transform into 16-, 8-, and 4-point matrix products according to the symmetric property of the transform coefficient. Moreover, we use the shift-and-add unit to share hardware resources between multiple transform dimension matrix products. The 1-D IDCT core can simultaneously calculate the first- and second-dimensional data. The results indicate that the proposed 2-D IDCT core has a throughput rate of 250 MP/s, with only 110 K gate counts when implemented into the Taiwan semiconductor manufacturing (TSMC) 90-nm complementary metal-oxide-semiconductor (CMOS) technology. The results show the proposed circuit has the smallest area supporting the multiple transform sizes.

Transpose

Discrete Hartley transform

10.1186/s13634-020-00708-0

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VLSI Implementation of a Cost-Efficient 3-Lead Lossless ECG Compressor and Decompressor

Circuits Systems and Signal Processing (2019)

Yuan‐Ho Chen Yun-Hua Tseng Pao‐Hsien Chu Yen Juan Shun-Ping Wang

Gate count

10.1007/s00034-019-01198-8

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Citations (3)

A Simplified Simulated Annealing Algorithm and Its Implementation

2022 IEEE 11th Global Conference on Consumer Electronics (GCCE) (2024)

William Cheng-Chung Cheng-Chung Chu Yuan‐Ho Chen

Adaptive simulated annealing

10.1109/gcce62371.2024.10760999

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Low-Complexity Bit-Parallel Systolic Multipliers over GF(2m)

Chiou‐Yng Lee Chin-Chin Chen Yuan‐Ho Chen Erl‐Huei Lu

Recently, cryptographic applications based on finite fields have attracted much interest. This paper presents two new algorithms, called time-dependent and time-independent multiplication algorithms over a finite field GF(2m) by employing an interleaved conventional multiplication and a folded technique. The proposed algorithms permit efficient realization of the bit-parallel multiplication using iterative arrays. The results show that our proposed time-dependent and time-independent multipliers save about 38% and 54% space complexity as compared to the traditional multipliers, respectively.

Realization (probability)

Multiplication algorithm

10.1109/icsmc.2006.384557

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A 10-Bit Low-Power High-Color-Depth Column Driver With Two-Stage Multi-Channel RDACs for Small-Format TFT-LCD Driver ICs

Journal of Display Technology (2015)

Ping-Yeh Yin Chih‐Wen Lu Yuan‐Ho Chen Hsin-Chin Liang Sheng-Pin Tseng

This study proposes a 10-bit low-power high-color-depth LCD column driver IC with two-stage multi-channel RDACs and switch resistance compensation. The design removes intermediate buffers from two-stage RDACs and uses global reference buffers to isolate the global resistor string and output channels. Because the global resistor string is isolated from output channels, the global resistor string can use a larger resistance value to achieve lower power consumption. This study proposes a class-AB buffer for the global reference buffers to compensate for the errors caused by the voltage drop on switches connected in series with the channel resistor string. The channel resistor strings also reuse the output stage current of the global buffer to reduce power consumption. A prototype of a 200-channel column driver was fabricated using 0.18- μm/0.35- μm CMOS technology with the worst DNL/INL being 1.2/1.1 LSB. The proposed 10-bit DAC occupies only 66% of the area of a conventional 8-bit RDAC using the same technology. The 200-channel column driver consumes a total static current of only 0.38 mA.

Voltage drop

10.1109/jdt.2015.2434414

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Citations (13)

High-Throughput Multistandard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic

IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2013)

Yuan‐Ho Chen Jyun-Neng Chen Tsin‐Yuan Chang Chih‐Wen Lu

This paper proposes a low-cost high-throughput multistandard transform (MST) core, which can support MPEG-1/2/4 (8 × 8), H.264 (8 × 8, 4 × 4), and VC-1 (8 × 8, 8 × 4, 4 × 8, 4 × 4) transforms. Common sharing distributed arithmetic (CSDA) combines factor sharing and distributed arithmetic sharing techniques, efficiently reducing the number of adders for high hardware-sharing capability. This achieves a 44.5% reduction in adders in the proposed MST, compared with the direct implementation method. With eight parallel computation paths, the proposed MST core has an eightfold operation frequency throughput rate. Measurements show that the proposed CSDA-MST core achieves a high-throughput rate of 1.28 G-pels/s, supporting the (4928 × 2048@24 Hz) digital cinema or ultrahigh resolution format. This is possible only with 30 k gate counts when implemented in a TSMC 0.18- μm CMOS process. The CSDA-MST core thus achieves a high-throughput rate supporting multistandard transformations at low cost.

10.1109/tvlsi.2013.2251021

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Citations (14)

Multiple Leads With a Switch Mode for Lossless and Lossy Compression Using Very-Large-Scale Integration Technology

IEEE Access (2018)

Yun-Hua Tseng Yuan‐Ho Chen Chih‐Wen Lu

Electrocardiogram monitoring is crucial for the prevention and treatment of cardiovascular diseases. In this paper, we developed a wearable device involving multiple leads that monitors cardiac electrical activity using very large-scale integration technology to facilitate long-term activity monitoring. In addition to using limb leads and augmented limb leads for monitoring heart activity, six unipolar chest leads were attached to six positive electrodes and placed on the surface of the chest to record electrical activity of different regions of the heart. The multiple leads lie perpendicular to the frontal plane and were integrated within a single circuit to reduce hardware costs and size of the device. The proposed architecture also allows users to switch between lossless and lossy compression to control the power consumption and bit compression ratio. The effectiveness of the proposed approach was verified by fabricating a chip using 0.18-

$\mu \text{m}$

CMOS technology. The proposed architecture core has an operating frequency of 41 MHz and a gate count of 4K.

Lossy compression

10.1109/access.2018.2879412

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Citations (1)