The use of brushless DC motors will increase with the transition of conventional vehicle motors to electric vehicles (Electric Vehicles). The purpose of this study is to produce control that can maintain and increase the stability of motor rotation at changing or non-linear loads. It then performs testing of the created model. The control method used is PID. The control that is suitable for use in cases like this is the PID (Proportional Integral Derivative) control system. The best K p , K i , and K d values obtained based on trial and error, and the values obtained are K p = 1.1, K i = 0.2, and K d = 0.8. The response to distractions gets better and the response to speed variations gets better. In addition, the speed of the simulation results can follow the change in the speed reference with a slight overshoot in each transition of the speed value. The resulting system responds with a settling time value of 0.0035 s and a large overshoot with a value of 1.9%.
This paper presents design of a programmable fuzzy logic controller and its implementation on a complex programmable logic device (CPLD) chip. This digital fuzzy logic controller (FLC) can be reconfigured in term of its antecedents or membership function parameters, fuzzy implication rules, and consequence parameters. Due to its programmable capability, this digital FLC is intended to be a general-two-dimensional fuzzy controller for several application areas. The digital FLC circuit is designed to be as flexible as possible, and thus the user finds it easy to utilize the FLC in control applications, which need real-time operations. The digital FLC is implemented on a CPLD chip using a VHDL-based synthesis model.
Traffic signs are one of the important road equipment facilities to inform road users about regulations and visual directions. Currently, an automatic Traffic Sign Recognition (TSR) system is being developed which is implemented in an advanced driver system (ADAS) so that road users can be safe and secure while on the road. Therefore, this paper aims to be able to detect and recognize traffic signs on the highway to provide information on the meaning of these traffic signs automatically. In this study, 35 classes of signs were used which consisted of warning signs, prohibitions signs, mandatory signs, and instructions signs. This system is implemented using the Darknet framework with the You Only Look Once version 4 (YOLOv4) model. The investigation carried out in this study is a system that detects and recognizes traffic signs evaluated on offline-based video in one-way traffic during the day. The result of mAP (mean Average Precision) in this system is 95.15%.
This paper presents an arbitration mechanism to balance bandwidth consumption or data throughputs between packets in a network-on-chip (NoC) with ID-based wormhole cut-through switching method. When data traffic flowing through a network communication link is high, the bandwidth space of the link, which is comsumed by a message or a data stream, could be affected by the distance between the source node, from which the message is injected, and the hotspot node. Without considering the number of stream flows from different input ports, a simple arbitration control such as round-robin arbitration cannot balance throughput between the streams. This paper proposes an arbitration control strategy capable of assigning bandwidth or data rate fairly between the data streams. The fair arbitration mechanism is enabled by which the arbiter units detect active requests from input ports and the number of the streams flowing from the input ports of the routers. By using the arbitration mechanism, a stream coming far from a hotspot node, can share bandwidths fairly with other streams nearby the the hotspot node.
This research presents a method for regulating varying voltage as a DC source in a six-step commutation brushless DC (BLDC) motor drive through control proportional integral derivative (PID) as a simple strategy for controlling the speed of BLDC motors. Strengthening the control gain uses the particle swarm optimization (PSO) algorithm by minimizing the root mean square error (RMSE) and overshoot as fitness control characteristics. The performance of the motor with the proposed controller is analyzed and compared with an experimentally-simulated-tuned PID, hybrid gray wolf optimization–proportional integral (GWO-PI), and hybrid horse herd PSO-PID (HHH PSO-PID) under changing load and speed conditions. Simulation using compose-psim altair software. Control system response parameters such as RMSE, overshoot, electromagnetic torque ripple, and phase current ripple are measured and compared with the above controllers. The results show that the proposed controller is superior to a wide range of predefined system responses.
A network-on-chip (NoC), having guaranteed-throughput (GT) or guaranteed bandwidth service by using a flexible method to establish a connection-oriented data communication at runtime, is presented in this paper. The GT packets can share communication link with a flexible manner, where flits belonging to the same packet will have the same local identity-tag (ID-tag). The ID-tags of each packet will vary locally along communication links, and are organized with an ID-tag mapping management unit, which is implemented at each output part of the on-chip routers. There is no need for a specific algorithm for finding a conflict-free scheduling as commonly used in the TDM-based methods that use time slots allocation technique. The contention problem is solved with the hardware solution based on the locally organized message identity (ID). This guaranteed bandwidth/throughput service will provide a good interconnect platform for many core processor systems running computer vision and multimedia applications with better performance.
This paper presents a comparative study of DC-DC converters with boost methods of several types of circuits that use PSPICE programming. The whole series is compared by analyzing the maximum Reinforcement stress produced. Measurement of efficiency is now added to the test. The simulation results show that the BCI circuit is able to produce the highest voltage based on testing using 12V and 24V input voltage variations. The output voltage is capable of producing a BCI 106.440 V circuit for 12V input, while a 24V BCI input produces an output voltage of 212,808 V. The efficiency calculation is obtained for the BCI circuit with an input voltage variation of 82,215 % - 82,287 %. Test based on duty cycle, BCI output voltage 363,967 V with a work cycle of 0.9 %. For load variations, this circuit produces an output voltage of 107,459 V with a duty cycle of 0.5 % and a load of 1KΩ. This research is a promising solution in the future as an effort to overcome the electricity energy crisis.
This paper presents design trade-off and performance impacts of the amount of pipeline phase of control path signals in a wormhole-switched network-on-chip (NoC). The numbers of the pipeline phase of the control path vary between twoand one-cycle pipeline phase. The control paths consist of the routing request paths for output selection and the arbitration paths for input selection. Data communications between on-chip routers are implemented synchronously and for quality of service, the inter-router data transports are controlled by using a link-level congestion control to avoid lose of data because of an overflow. The trade-off between the area (logic cell area) and the performance (bandwidth gain) of two proposed NoC router microarchitectures are presented in this paper. The performance evaluation is made by using a traffic scenario with different number of workloads under 2D mesh NoC topology using a static routing algorithm. By using a 130-nm CMOS standard-cell technology, our NoC routers can be clocked at 1 GHz, resulting in a high speed network link and high router bandwidth capacity of about 320 Gbit/s. Based on our experiments, the amount of control path pipeline stages gives more significant impact on the NoC performance than the impact on the logic area of the NoC router. Keywords—Network-on-Chip, Synchronous Parallel Pipeline, Router Architecture, Wormhole Switching
A synchronous network-on-chip using wormhole packet switch- ing and supporting guaranteed-completion best-effort with low-priority (LP) and high-priority (HP) wormhole packet delivery service is presented in this paper. Both our proposed LP and HP message services deliver a good quality of service in term of lossless packet completion and in-order message data delivery. However, the LP message service does not guarantee minimal completion bound. The HP packets will absolutely use 100% bandwidth of their reserved links if the HP packets are injected from the source node with maximum injection. Hence, the service are suitable for small size messages (less than hundred bytes). Otherwise the other HP and LP messages, which require also the links, will experience relatively high latency depending on the size of the HP message. The LP packets are routed using a minimal adaptive routing, while the HP packets are routed using a non-minimal adaptive routing algorithm. Therefore, an additional 3-bit field, identifying the packet type, is introduced in their packet headers to classify and to determine the type of service committed to the packet. Our NoC prototypes have been also synthesized using a 180-nm CMOS standard-cell technology to evaluate the cost of implementing the combination of both services.
