Babak Falsafi

École Polytechnique Fédérale de Lausanne

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Burton Smith

Microsoft (United States)

Thomas F. George

Kerala Agricultural University

Bernard Philippe

Institut national de recherche en informatique et en automatique

JackB Dennis

Massachusetts Institute of Technology

Tryggve Fossum

Intel (United Kingdom)

François Irigoin

Centre de Recherche en Informatique

Christof Klausecker

Ludwig-Maximilians-Universität München

Joefon Jann

IBM Research - Thomas J. Watson Research Center

Marc Snir

University of Illinois Urbana-Champaign

Samuel P. Midkiff

Purdue University West Lafayette

Cooperative Institutions

Carnegie Mellon University

École Polytechnique Fédérale de Lausanne

Intel (United States)

University of Wisconsin–Madison

The University of Texas at Austin

IBM (United States)

University of Michigan–Ann Arbor

University of Illinois Urbana-Champaign

Purdue University West Lafayette

Microsoft (United States)

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SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators

arXiv (Cornell University) (2020)

Javier Picorel Seyed Alireza Sanaee Kohroudi Yan Zi Abhishek Bhattacharjee Babak Falsafi

Virtual memory (VM) is critical to the usability and programmability of hardware accelerators. Unfortunately, implementing accelerator VM efficiently is challenging because the area and power constraints make it difficult to employ the large multi-level TLBs used in general-purpose CPUs. Recent research proposals advocate a number of restrictions on virtual-to-physical address mappings in order to reduce the TLB size or increase its reach. However, such restrictions are unattractive because they forgo many of the original benefits of traditional VM, such as demand paging and copy-on-write. We propose SPARTA, a divide and conquer approach to address translation. SPARTA splits the address translation into accelerator-side and memory-side parts. The accelerator-side translation hardware consists of a tiny TLB covering only the accelerator's cache hierarchy (if any), while the translation for main memory accesses is performed by shared memory-side TLBs. Performing the translation for memory accesses on the memory side allows SPARTA to overlap data fetch with translation, and avoids the replication of TLB entries for data shared among accelerators. To further improve the performance and efficiency of the memory-side translation, SPARTA logically partitions the memory space, delegating translation to small and efficient per-partition translation hardware. Our evaluation on index-traversal accelerators shows that SPARTA virtually eliminates translation overhead, reducing it by over 30x on average (up to 47x) and improving performance by 57%. At the same time, SPARTA requires minimal accelerator-side translation hardware, reduces the total number of TLB entries in the system, gracefully scales with memory size, and preserves all key VM functionalities.

Translation lookaside buffer

Page

10.48550/arxiv.2001.07045

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Citations (1)

The HiPEAC Vision

Albert Cohen Marc Duranton Sami Yehia Bjorn De Sutter Koen De Bosschere

The HiPEAC roadmap describes the HiPEAC vision on high-performance embedded architecture and compilation for the coming decade. It starts from societal challenges, application and industry trends, and technological constraints which lead to 7 technical challenges. This forms the basis for the HiPEAC vision keep it simple for humans, and let the computer do the hard work and its consequences. The roadmap ends with a SWOT analysis of the computing systems industry in Europe, and 6 research recommendations.

SWOT Analysis

Technology roadmap

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Citations (34)

Sirocco: cost-effective fine-grain distributed shared memory

I. Schoinas Babak Falsafi M.D. Hill J.R. Larus David A. Wood

Software fine-grain distributed shared memory (FGDSM) provides a simplified shared-memory programming interface with minimal or no hardware support. Originally software FGDSMs targeted uniprocessor-node parallel machines. This paper presents Sirocco, a family of software FGDSMs implemented on a network of low-cost SMPs. Sirocco takes full advantage of SMP nodes by implementing inter-node sharing directly in hardware and overlapping computation with protocol execution. To maintain correct shared-memory semantics, however SMP nodes require mechanisms to guarantee atomic coherence operations. Multiple SMP processors may also result in contention for shared resources and reduce performance. SMP nodes also impact the cost trade-off. While SMPs typically charge higher price-premiums, for a given system size SMP nodes substantially reduce networking hardware requirement as compared to uniprocessor nodes. In this paper, we ask the question "Are SMPs cost-effective building blocks for software FGDSM?" We present experimental measurements on Sirocco implementations ranging from an all-software system to a system with minimal hardware support. Together with simple cost models we show that low-cost SMP nodes: (i) result in competitive performance with uniprocessor nodes, (ii) substantially reduce hardware requirement and are more cost-effective than uniprocessor nodes, (iii) significantly benefit from hardware support for coherence operations, and (iv) are especially beneficial for FGDSMs with high-overhead coherence operations.

Uniprocessor system

Distributed memory

10.1109/pact.1998.727144

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Citations (7)

Architecture-conscious databases

Babak Falsafi Jignesh M. Patel Ken Ross

No abstract available.

10.1145/1114252.1114266

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Citations (3)

Fine-grain access control for distributed shared memory

Ioannis Schoinas Babak Falsafi Alvin R. Lebeck Steven K. Reinhardt James R. Larus

This paper discusses implementations of fine-grain memory access control, which selectively restricts reads and writes to cache-block-sized memory regions. Fine-grain access control forms the basis of efficient cache-coherent shared memory. This paper focuses on low-cost implementations that require little or no additional hardware. These techniques permit efficient implementation of shared memory on a wide range of parallel systems, thereby providing shared-memory codes with a portability previously limited to message passing.

Distributed shared memory

Software portability

Implementation

Distributed memory

Cache-only memory architecture

10.1145/195473.195575

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Citations (269)

Program Committee

André Seznec Aamer Jaleel Nvidia Bhattacharjee Ahmed Louri Alvin R. Lebeck

10.1109/isca.2016.8

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Citations (0)

From embedded multi-core SoCs to scale-out processors

Marcello Coppola Babak Falsafi John Goodacre George Kornaros

Information technology is now an indispensable pillar of a modern day society. CMOS technologies, which lay the foundation for all digital platforms, however, are experiencing a major inflection point due to a slowdown in voltage scaling. The net result is that power is emerging as the key design constraint for all platforms from embedded systems to datacenters. This tutorial presents emerging design paradigms from embedded multicore SoCs to server processors for scale-out datacenters based on mobile cores.

Multi-core processor

Moore's law

10.5555/2485288.2485516

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Citations (6)

Reunion: Complexity-Effective Multicore Redundancy

Proceedings of the ... annual International Symposium on Microarchitecture/Proceedings of the annual International Symposium on Microarchitecture (2006)

Jared C. Smolens Brian T. Gold Babak Falsafi Juanita Hoe

To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identical instruction streams is challenging because redundant cores operate independently, yet must still receive the same inputs (e.g., load values and shared-memory invalidations). Past proposals strictly replicate load values across two cores, requiring significant changes to the highly-optimized core. We make the key observation that, in the common case, both cores load identical values without special hardware. When the cores do receive different load values (e.g., due to a data race), the same mechanisms employed for soft error detection and recovery can correct the difference. This observation permits designs that relax input replication, while still providing correct redundant execution. In this paper, we present Reunion, an execution model that provides relaxed input replication and preserves the existing memory interface, coherence protocols, and consistency models. We evaluate a CMP-based implementation of the Reunion execution model with full-system, cycle-accurate simulation. We show that the performance overhead of relaxed input replication is only 5% and 6% for commercial and scientific workloads, respectively

Multi-core processor

Replication

Cache coherence

10.1109/micro.2006.42

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Citations (147)

A community effort in SARS‐CoV‐2 drug discovery

Molecular Informatics (2023)

Johannes Schimunek Philipp Seidl Katarina Elez Tim Hempel Tuan Anh Le

The COVID-19 pandemic continues to pose a substantial threat to human lives and is likely to do so for years to come. Despite the availability of vaccines, searching for efficient small-molecule drugs that are widely available, including in low- and middle-income countries, is an ongoing challenge. In this work, we report the results of an open science community effort, the "Billion molecules against COVID-19 challenge", to identify small-molecule inhibitors against SARS-CoV-2 or relevant human receptors. Participating teams used a wide variety of computational methods to screen a minimum of 1 billion virtual molecules against 6 protein targets. Overall, 31 teams participated, and they suggested a total of 639,024 molecules, which were subsequently ranked to find 'consensus compounds'. The organizing team coordinated with various contract research organizations (CROs) and collaborating institutions to synthesize and test 878 compounds for biological activity against proteases (Nsp5, Nsp3, TMPRSS2), nucleocapsid N, RdRP (only the Nsp12 domain), and (alpha) spike protein S. Overall, 27 compounds with weak inhibition/binding were experimentally identified by binding-, cleavage-, and/or viral suppression assays and are presented here. Open science approaches such as the one presented here contribute to the knowledge base of future drug discovery efforts in finding better SARS-CoV-2 treatments.

10.1002/minf.202300262

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Citations (7)

Sirocco: cost-effective fine-grain distributed shared memory

International Conference on Parallel Architectures and Compilation Techniques (1998)

Ioannis Schoinas Babak Falsafi Mark D. Hill James R. Larus David A. Wood

Software fine-grain distributed shared memory (FGDSM) provides a simplified shared-memory programming interface with minimal or no hardware support. Originally software FGDSMs targeted uniprocessor-node parallel machines. This paper presents Sirocco, a family of software FGDSMs implemented on a network of low-cost SMPs. Sirocco takes full advantage of SMP nodes by implementing inter-node sharing directly in hardware and overlapping computation with protocol execution. To maintain correct shared-memory semantics, however SMP nodes require mechanisms to guarantee atomic coherence operations. Multiple SMP processors may also result in contention for shared resources and reduce performance. SMP nodes also impact the cost trade-off. While SMPs typically charge higher price-premiums, for a given system size SMP nodes substantially reduce networking hardware requirement as compared to uniprocessor nodes. In this paper, we ask the question Are SMPs cost-effective building blocks for software FGDSM? We present experimental measurements on Sirocco implementations ranging from an all-software system to a system with minimal hardware support. Together with simple cost models we show that low-cost SMP nodes: (i) result in competitive performance with uniprocessor nodes, (ii) substantially reduce hardware requirement and are more cost-effective than uniprocessor nodes, (iii) significantly benefit from hardware support for coherence operations, and (iv) are especially beneficial for FGDSMs with high-overhead coherence operations.

Uniprocessor system

Distributed memory

10.5555/522344.825683

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Citations (31)