Chakry Srinivasa Varun Patnam

SRM University

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E. Chitra

SRM Institute of Science and Technology

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SRM Institute of Science and Technology

SRM University

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EFFICIENT FPGA REALIZATION OF DA-BASED RECONFIGURABLE FIR DIGITAL FILTER

Chakry Srinivasa Varun Patnam E. Chitra

This paper presents efficient distributed arithmetic (DA)-based approaches for high-throughput reconfigurable implementation of finite impulse response (FIR) filters whose filter coefficients change during runtime. Conventionally, for reconfigurable DA-based implementation of FIR filter, the lookup tables (LUTs) are required to be implemented in RAM; and the RAM-based LUT is found to be costly .Therefore, a shared-LUT design is proposed to realize the DA computation. Instead of using separate registers to store the possible results of partial inner products for DA processing of different bit positions, registers are shared by the DA units for bit slices of different weightage. The proposed design has nearly less area-delay product, when compared to DA-based conventional structure

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Finite impulse response

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