Shengdong Hu

Chongqing University

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Jingwei Guo

Shandong University

Zhi Lin

Chongqing University

Hao Wu

Chongqing University

Bo Zhang

University of Electronic Science and Technology of China

Ping Li

University of Electronic Science and Technology of China

Zhaoji Li

University of Electronic Science and Technology of China

Fang Tang

Chongqing University

Jianlin Zhou

Chongqing University

Jun Luo

Xi'an Jiaotong University

Ye Huang

University of Chinese Academy of Sciences

Cooperative Institutions

Chongqing University

Chinese Academy of Sciences

University of Electronic Science and Technology of China

National Engineering Research Center of Electromagnetic Radiation Control Materials

Zhejiang University

University of Chinese Academy of Sciences

China Electronic Product Reliability and Environmental Test Institute

Xidian University

Ministry of Industry and Information Technology

China Electronics Technology Group Corporation

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A novel analytical model of the vertical breakdown voltage on impurity concentration in top silicon layer for SOI high voltage devices

International Journal of Electronics (2011)

Shengdong Hu Bo Zhang Zhaoji Li

A novel analytical model of the vertical breakdown voltage (VB , V ) on impurity concentration (Nd ) in top silicon layer for silicon on insulator high voltage devices is first presented in this article. Based on an effective ionisation rate considering the multiplication of threshold energy εT in the electron, a new formula of silicon critical electric field ES , C on Nd is derived by solving a 2D Poisson equation, which increases with the increase in Nd especially at higher impurity concentration, and reaches up to 68.8 V/µm with Nd = 1 × 1017 cm−3 and 157.2 V/µm with Nd = 1 × 1018 cm−3 from the conventional about 30 V/µm, respectively. A new physical concept of critical energy εB is introduced to explain the mechanism of variable high ES , C with heavy impurity concentration. From the ES , C , the expression of VB , V is obtained, which is improved with the increasing Nd due to the enhanced ES , C. VB , V with a dielectric buried layer thickness (tI ) of 2 µm increases from 428 V of 1 × 1017 cm−3 to 951 V of 1 × 1018 cm−3. The dependence of Nd and top silicon layer thickness (tS ) for an optimised device is discussed. 2D simulations and some experimental results are in good agreement with the analytical results.

Poisson's equation

10.1080/00207217.2011.576598

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Citations (9)

A novel complementary N⁺-charge island SOI high voltage device

Journal of Semiconductors (2010)

Lijuan Wu Shengdong Hu Bo Zhang Zhaoji Li

A new complementary interface charge island structure of SOI high voltage device (CNI SOI) and its model are presented. CNI SOI is characterized by equidistant high concentration n+ -regions on the top and bottom interfaces of dielectric buried layers. When a high voltage is applied to the device, complementary hole and electron islands are formed on the two n+-regions on the top and bottom interfaces. The introduced interface charges effectively increase the electric field of the dielectric buried layer (EI) and reduce the electric field of the silicon layer (ES), which result in a high breakdown voltage (BV). The influence of structure parameters and its physical mechanism on breakdown voltage are investigated for CNI SOI. EI = 731 V/μm and BV = 750 V are obtained by 2D simulation on a 1-μm-thick dielectric layer and 5-μm-thick top silicon layer. Moreover, enhanced field EI and reduced field ES by the accumulated interface charges reach 641.3 V/μm and 23.73 V/μm, respectively.

10.1088/1674-4926/31/11/114010

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Citations (3)

Bipolar Degradation of SiC MOSFET Body Diode Under Constant Current Stress

Zijun Cheng Mingen Lv Dongsheng Zhao Shengdong Hu Yijun Shi

Degradation

Constant current

Constant (computer programming)

10.1109/icept63120.2024.10668409

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Citations (0)

A low specific on-resistance power trench MOSFET with a buried-interface-drain

Superlattices and Microstructures (2015)

Shengdong Hu Yinhui Chen Jingjing Jin Jianlin Zhou Feng Zhou

Power MOSFET

Figure of Merit

10.1016/j.spmi.2015.05.030

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Citations (12)

Radiation-Hardened CMOS Negative Voltage Reference for Aerospace Application

IEEE Transactions on Nuclear Science (2017)

Fan Liu Yang Feng Han Wang Xun Xiang Xichuan Zhou

Voltage reference is the key module in analog and mixed-signal integrated circuits. This paper presents a radiation-hardened CMOS negative voltage reference for aerospace electronics. To improve the antiradiation performance, in the circuit design, the input pair of the operational amplifier is replaced from pMOS to nMOS. An extra unity-gain amplification stage is added and the compensation network is optimized. Besides, the start-up circuit is redesigned. In the layout design, the annular-gate structure is adopted to eliminate electric leakage, while the layout technique against single-event latch-up is also used. The prototype of the proposed circuit is fabricated using a bulk CMOS 0.6-μm process with a 547 μm × 618 μm chip area. By using the proposed circuit and layout optimizations, the measured temperature coefficient of reference is reduced to 13 ppm/°C and the output voltage drift is below 1.2% after 300-krad(Si) total ionizing dose. The measured single-event latch-up threshold is above 94.6 MeVcm ² /mg.

Radiation hardening

10.1109/tns.2017.2733738

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Citations (10)

A Novel Approach to Suppress the Inhomogeneous Reverse Recovery Behavior of the Body Diode in Superjunction MOSFET

2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) (2022)

Ping Li Rongyao Ma Zhiyu Yang Jingwei Guo Zhi Lin

In this paper, a novel approach to suppress the inhomogeneous reverse recovery behavior of the body diode in Superjunction MOSFET is proposed and experimentally demonstrated. It features a heavily doped P-type region embedded in the interface of the termination region. When the Superjucntion MOSFET goes through the reverse recovery period, the heavily doped P-type region accelerates the extraction of the non-equilibrium hole carriers. As a result, the reverse recovery current of the termination region is reduced significantly, which is of great benefit in improving the dI/dt robustness. Experimental results show that by adopting the proposed approach, the dI/dt robustness during the reverse recovery could be improved from 123 A/μs to 1150 A/μs.

Robustness

10.1109/icsict55466.2022.9963356

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Experimental and Theoretical Demonstration of Temperature Limitation for 4H-SiC MOSFET During Unclamped Inductive Switching

IEEE Journal of Emerging and Selected Topics in Power Electronics (2019)

Junjie An Shengdong Hu

This article focuses on the avalanche energy handing ability and theoretical demonstration of the avalanche failure mechanism for the SiC MOSFET by the unclamped inductive switching (UIS) test, the mathematical model, and the numerical simulation. Two evaluation methods are implemented to understand the effect of the avalanche current density and the avalanche energy on the device failure with the ambient temperature ranging from 300 to 450 K. Moreover, the thermodynamic model based on the thermal diffusion equation is developed to explore the critical temperature limitation. The avalanche capability highly depends on the dimension parameters and premature degradation points. The numerical simulation with the multicells and the real device parameters is used to reveal the electric performances of the SiC MOSFET during the UIS for the first time. At the same time, the temperatures in the SiC lattice and the metal system are precisely separated by the numerical method. The experimental results and simulation study demonstrate that the molten metal system on the surface of the SiC MOSFET induced by the local high temperature is prone to generate the thermal stresses and damage the device during the UIS transient. This failure mechanism is perfectly supported by the experimental, modeling, and numerical results.

Transient (computer programming)

Avalanche breakdown

Switching time

10.1109/jestpe.2019.2944167

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Citations (45)

Breakdown voltage improvement of enhancement mode AlGaN/GaN HEMT by a novel step-etched GaN buffer structure

Results in Physics (2021)

Hao Wu Fu Xiaojun Yuan Wang Jingwei Guo Jingyu Shen

A research on breakdown voltage improvement of the enhancement mode (E-mode) AlGaN/GaN high electron mobility transistor (HEMT) has been carried out. A novel step-etched GaN buffer structure combined with a thin GaN buffer is studied by simulating. Both the thin GaN buffer and the step-etched GaN structure can improve the breakdown voltage. The thin GaN buffer can reduce the conductivity as well as alleviate the vertical electric field. And the step-etched GaN structure can form two electric field peaks and thus decrease the original one. With the same gate-drain length of 7 μm, the optimized structure increases the breakdown voltage from 316 V to 1487 V, and the specific on-state resistance is obtained to be 2.718 mΩ•cm2 which is the similar to conventional GaN HEMT, and the calculated FOM is improved by more than 20 times. These results indicate that the novel step-etched GaN buffer structure can improve the breakdown voltage without compromising the output characteristics.

Buffer (optical fiber)

Wide-bandgap semiconductor

10.1016/j.rinp.2021.104768

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Citations (16)

Study on the C _OSS Dynamic Loss of Superjunction MOSFETs in Quasi-Resonant Flyback Converters

IEEE Transactions on Electron Devices (2023)

Wei Zeng Ping Li Zhi Lin Da Wang Jingwei Guo

In this article, we study the output capacitance dynamic loss,

${E}_{\text {DISS}}$

, of superjunction (SJ) MOSFETs in the quasi-resonant (QR) flyback converter for the first time. A calorimetric method is used to measure

${E}_{\text {DISS}}$

of different SJ MOSFETs and numerical simulations are used to explore the electrothermal behavior of

${C}_{\text {OSS}}$

in OFF-state SJ MOSFETs. Based on measured results, we find that the RC buffer can reduce

${E}_{\text {DISS}}$

, and the more advanced the device is, the more effective the RC buffer is. Based on simulated results, we find that

${E}_{\text {DISS}}$

is mainly caused by the carrier movements in the lightly doped drift region during the charging and discharging processes. Each device has a critical voltage,

${V}_{\mathrm {DS\_{}CRL}}$

. If the minimal resonant drain voltage,

${V}_{\mathrm {DS\_{}MIN}}$

, is lower than

${V}_{\mathrm {DS\_{}CRL}}$

, the neutral islands can be merged and a large current density occurs in the channel, leading to increased

${E}_{\mathrm {DISS}}$

. If

${V}_{\mathrm {DS\_{}MIN}}$

is higher than

${V}_{\mathrm {DS\_{}CRL}}$

${E}_{\mathrm {DISS}}$