Shimeng Yu

Georgia Institute of Technology

Author Statistics

Papers

Citation

H-Index

i-10 index

Research Trends

Author Order

Document Type

Co-Authors

Asif Islam Khan

Georgia Institute of Technology

Xiaochen Peng

Georgia Institute of Technology

H.‐S. Philip Wong

Stanford University

Pai-Yu Chen

Arizona State University

Suman Datta

Georgia Institute of Technology

Jae Hur

Intel (United States)

Bin Gao

University of Shanghai for Science and Technology

Jae-sun Seo

Cornell University

Yuan-Chun Luo

Georgia Institute of Technology

Yandong Luo

Georgia Institute of Technology

Cooperative Institutions

Georgia Institute of Technology

141

Lawrence Berkeley National Laboratory

124

Lawrence Livermore National Laboratory

108

University of California, Berkeley

Los Alamos National Laboratory

Stanford University

Peking University

Institute of Microelectronics

Massachusetts Institute of Technology

Tsinghua University

Author Statistics

Papers

Citation

H-Index

i-10 index

Research Field

Compute-in-Memory with Emerging Nonvolatile-Memories: Challenges and Prospects

2022 IEEE Custom Integrated Circuits Conference (CICC) (2020)

Shimeng Yu Xiaoyu Sun Xiaochen Peng Shanshi Huang

This invited paper surveys the recent progresses of compute-in-memory (CIM) prototype chip designs with emerging nonvolatile memories (eNVMs) such as resistive random access memory (RRAM) technology. 8kb to 4Mb CIM mixed-signal macros (with analog computation within the memory array) have been demonstrated by academia and industry, showing promising energy efficiency and throughput for machine learning inference acceleration. However, grand challenges exist for large-scale system design including the following: 1) substantial analog-to-digital (ADC) overhead; 2) scalability to advanced logic node limited by high write voltage of eNVMs; 3) process variations (e.g. ADC offset) that degrade the inference accuracy. Mitigation strategies and possible future research directions are discussed.

Non-Volatile Memory

Phase-change memory

10.1109/cicc48029.2020.9075887

Cite

Citations (57)

Local epitaxial-like templating effects and grain size distribution in atomic layer deposited Hf0.5Zr0.5O2 thin film ferroelectric capacitors

Applied Physics Letters (2021)

Sarah Lombardo Mengkun Tian Kisung Chae Jae Hur Nujhat Tasneem

The microstructure in fluorite-structure oxide-based ferroelectric thin films, especially when on standard semiconductor manufacturing platforms, is poly-/nano-crystalline, which controls the functionality, performance, and reliability of the device technologies based on them. Understanding the relationships between microstructure, process, and performance for this class of materials has remained challenging. Here, a systematic approach is presented for analyzing and visualizing grains, their size distributions, and interlayer templating effects in ferroelectric thin film systems by utilizing an advanced microscopy technique, namely nanobeam electron diffraction, coupled with dark-field transmission electron microscopy and atomic resolution scanning transmission electron microscopy. A 10 nm TiN/10 nm Hf0.5Zr0.5O2 (HZO)/10 nm TiN ferroelectric heterostructure is probed. A geometric mean of the grain size in HZO of 26.8 nm ranging from 5 to 95 nm with top and bottom TiN layers having a much smaller grain size of approximately 6.8 nm ranging from 3 to 17 nm is observed. Furthermore, there is evidence of templating effects between HZO and TiN grain and domain boundaries showing [111] and [001] growth directions locally for HZO and TiN, respectively.

10.1063/5.0057782

Cite

Citations (17)

Variability Induced by Line Edge Roughness in Double-Gate Dopant-Segregated Schottky MOSFETs

IEEE Transactions on Nanotechnology (2009)

Yunxiang Yang Shimeng Yu Lang Zeng Gang Du Jinfeng Kang

Intrinsic parameter fluctuations introduced by process variations, such as line edge roughness (LER), create an increasing challenge to the CMOS technology scaling. In this paper, variations in double-gate dopant-segregate Schottky (DSS) MOSFETs, caused by LER of silicon-fin, are systematically investigated using statistical technology computer-aided design simulations. The impact of LER on both Schottky barrier and DSS-MOSFETs are examined contrastively. The results show that DSS-MOSFETs offer a larger and more uniform drive current, but suffer a more serious V t fluctuation. The cause of such larger V t flutuation is also analyzed, thus providing a good starting point to propose way to solve this problem.

Line (geometry)

10.1109/tnano.2009.2037222

Cite

Citations (4)

Ferroelectric Gate Stack Engineering with Tunnel Dielectric Insert for Achieving High MemoryWindow in FEFETs for NAND Applications

Dipjyoti Das Hyeonwoo Park Zekai Wang Chengyang Zhang Prasanna Venkatesan Ravindran

We experimentally demonstrate a novel gate stack engineering technique by introducing a Tunnel Dielectric Layer (TDL) between two Ferroelectric (FE) layers, significantly increasing the Memory Window (MW) in FEFETs. An $\gt 2 \mathrm{X}$ improvement, from $2.9 \mathrm{~V}$ in the reference device (without TDL) to $7.5 \mathrm{~V}$ in the $8 / 3 / 8$ configuration with TDL, was achieved within NAND thickness limit of $20 \mathrm{~nm}$ and write voltage $\leq 15 \mathrm{~V}$. Impact of FE and TDL thickness in MW was also explored.

10.1109/edtm58488.2024.10511400

Cite

Citations (2)

3-D simulation of geometrical variations impact on nanoscale FinFETs

Shimeng Yu Yuning Zhao Yuncheng Song Gang Du Jinfeng Kang

Intra-die fluctuations in the nanoscale CMOS technology emerge inherently to geometrical variations such as line edge roughness (LER) and oxide thickness fluctuations (OTF). A full 3-D statistical simulation is presented to investigate the impact of geometrical variations on the FinFETs performance. In this work, roughness is introduced by a Fourier analysis of the power spectrum of Gaussian autocorrelation function. The influence of different geometrical variation sources is compared and summarized. The results shows that FinFETs performance is most sensitive to the fin LER, which causes a remarkable shift and fluctuations in threshold voltage, drain induced barrier lower effect (DIBL) and leakage current. The impact of gate LER follows that of fin LER. The simulation also suggests quantum confinement effect accounts for the aggressive fluctuations due to fin LER.

Drain-induced barrier lowering

Fin

10.1109/icsict.2008.4734551

Cite

Citations (15)

A Versatile ReRAM-based Accelerator for Convolutional Neural Networks

Manqing Mao Xiaoyu Sun Xiaochen Peng Shimeng Yu Chaitali Chakrabarti

Though recent progress in resistive random access memory (ReRAM)-based accelerator designs for convolutional neural networks (CNN) achieve superior timing performance and area-efficiency improvements over CMOS-based accelerators, they have high energy consumptions due to low inter-layer data reuse. In this work, we propose a multi-tile ReRAM accelerator for supporting multiple CNN topologies, where each tile processes one or more layers in a pipelined fashion. Building upon the fact that a tile with large receptive field can be built with a stack of smaller (3×3) filters, we design every tile with 9 processing elements that operate in a systolic fashion. Use of systolic data flow design maximizes input feature map reuse and minimizes interconnection cost. We show that 1-bit weight and 4-bit activation achieves good accuracy for both AlexNet and VGGNet, and design our ReRAM based accelerator to support this configuration. System-level simulation results on 32 nm node show that the proposed architecture for AlexNet with stacking small filters can achieve computation efficiency of 8.42 TOPs/s/mm ² , energy efficiency of 4.08 TOPs/s/W and storage efficiency of 0.18 MB/ mm ² for inference computation of one image in the CIFAR-100 dataset.

10.1109/sips.2018.8598372

Cite

Citations (7)

Static Random Access Memory (SRAM)

CRC Press eBooks (2022)

Shimeng Yu

Random access

10.1201/9781003138747-2

Cite

Citations (1)

Cryo-CMOS design-technology co-optimization of low noise amplifier for silicon qubit readout

Microelectronic Engineering (2022)

Dongsuk Kang Shimeng Yu

Power–delay product

10.1016/j.mee.2022.111837

Cite

Citations (4)

A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) (2021)

Wantong Li Xiaoyu Sun Hongwu Jiang Shanshi Huang Shimeng Yu

Resistive random access memory (RRAM) based compute-in-memory (CIM) has shown great potentials for deep neural network (DNN) inference. Prior works generally used off-chip write-verify scheme to tighten the RRAM resistance distribution and used off-chip analog-to-digital converter (ADC) references to fine-tune partial sum quantization edges. Though off-chip techniques are viable for testing purposes, they are unsuitable for practical applications. This work presents an RRAM-CIM macro that features 1) on-chip write-verify to speed up initial weight programming and periodically refresh cells to compensate for resistance drift under stress, and 2) on-chip ADC reference generation that provides column-wise tunability to mitigate offsets induced by process variation to guarantee CIFAR-10 accuracy of >90%. The design is taped-out in TSMC N40 RRAM process, and achieves 36.4TOPS/W for 1×1b MAC operations on VGG-8 network.

Macro

Data retention

Process Variation

10.1109/esscirc53450.2021.9567844

Cite

Citations (14)

Overview of inertial fusion research in the United States

Nuclear Fusion (2007)

T. C. Sangster R. L. McCrory V. N. Goncharov D. R. Harding S. J. Loucks

The inertial confinement fusion (ICF) programme, the high-average-power lasers (HAPL) programme, and the heavy ion fusion (HIF) programme are making long-term investments to establish the scientific and technical basis for an economically and environmentally attractive fusion power source. In the near term, the National Ignition Campaign is expected to establish the scientific and technical basis for ignition and gain on the National Ignition Facility. The results of these experiments and the implications for target design will be incorporated into the long-term efforts to develop a viable power-plant concept including target production, chamber dynamics and driver.

National Ignition Facility

Fusion power

10.1088/0029-5515/47/10/s17

Cite

Citations (28)