Illumination dependence of the standing wave effect was investigated by experiment and simulation in variously sized line and space (L&S) patterns. A chemically amplified positive resist and a KrF excimer laser stepper with 0.5 N A (numerical aperture) were used under various defocus conditions. The amplitude of the swing curve increased with increasing defocus value and showed complicated illumination dependence. At a focused position, higher σ (partial coherence) and oblique illuminations induced a larger amplitude of the swing curve; however, in the defocused region of ±0.6 µ m, necessary for actual device fabrication, the amplitudes of these illuminations were smaller than that of low σ illumination. Moreover, it was found that the amplitude variation was closely related to the log-slope value of exposure light intensity distribution at the nominal pattern edge.
We report on the reduction of the mask 3D effect in an etched 40-pair multilayer extreme ultraviolet (EUV) lithography mask by measuring the printed ΔCD (horizontal–vertical) on exposure with a high-NA small field exposure tool (HSFET). We compared these patterns with those of a conventional Ta-based absorber EUV lithography mask. Next, we examined the programmed pattern defect printability of the etched 40-pair multilayer EUV lithography mask and showed that defect printability of the etched multilayer mask was hardly influenced by the direction of EUV illumination. We conclude that the mask 3D effect reduction contributes to simple specifications of the mask pattern defect printability in EUV lithography.
To satisfy the tight budget of critical dimension, an immersion exposure process is widely applied to critical layers of the recent advanced devices to accomplish the high performance of resolution. In our 40nm node logic devices, the overlay accuracy of the critical layers (immersion to immersion) would be required to be less than 15nm (Mean+3sigma) and the one of the sub-critical layers (dry to immersion) would be required to be less than 20nm (Mean+3sigma). Furthermore, the overlay accuracy of the critical layers might be less than 10nm (Mean+3sigma) in the 32nm node logic devices. The method of improving the overlay performance should be investigated for mass production in the future. In this report, attaching weight to productivity, we selected the technique of high order process correction with machine configuration and applied it for 40 nm node production. We evaluated the overlay performance of the critical layers using 40nm process stack wafer and found that high order grid compensation was effective for reducing the process impact on the overlay accuracy. Furthermore, about the sub-critical layers, high order grid compensation was also effective for controlling the tool matching error.
Resist process challenges for 32-nm node and beyond are discussed in this paper. For line and space (L/S) logic patterns, we examine ways to balance the requirements of resolution-enhancement techniques (RETs). In 32-nm node logic patterning, two-dimensional (2D) layout pattern deformation becomes more severe with stronger RET (e.g., narrow angle CQUAD illumination). Also pattern collapse more frequently happens in 2D-pattern layouts when stronger RET is used. In contrast, milder RET (annular illumination) does not induce the severe pattern collapse in 2D-pattern layout. For 2D-pattern layouts, stronger RET seems to worsen image contrast and results in high background-light in the resist pattern, which induces more pattern collapse. For the minimum-pitch L/S pattern in 32-nm node logic, annular illumination is acceptable for patterning with NA1.35 scanner when high contrast resist is used. For contact/via patterns, it is necessary to expand the overlapping CD process window. Better process margin is realized through the combination of hole-shrink technique and precise acid-diffusion control in an ArF chemically amplified resist.
As a platform for active nanophotonics, localized surface plasmon resonance (LSPR) switching via interaction with a chalcogenide phase change material (GeSbTe) was investigated. We performed single-particle spectroscopy of gold nanoparticles placed on a GeSbTe thin film. By irradiation with a femtosecond pulsed laser for amorphization and a continuous wave laser for crystallization, significant switching behavior of the LSPR band due to the interaction of GeSbTe was observed. The switching mechanism was explained in terms of both a change in the refractive index and a modification of surface morphology accompanying volume expansion and reduction of GeSbTe.
Here we present both simulation and experimental results that show the effect of changes in laser light source bandwidth (E95) on CD Iso-Dense Bias. For the 55nm Technology Node Device, we have shown that E95 stability of less than 0.11pm is required in order to maintain OPE variation to within 2nm. In addition, we also verified another method to adjust for OPE variations that occur when E95 fluctuates. The Contrast Adjustment method is an effective function to adjust for OPE variation due to E95 fluctuation; it has been shown to maintain OPE variation less than 1.5nm. Furthermore, for the 45nm Technology Node Device, we have demonstrated that E95 stability of less than 0.07pm is required to maintain OPE variation to within 1nm. The bandwidth performance of the latest laser light source exhibits E95 stability less than 0.03 pm, thereby showing that the OPE variation due to E95 can be kept to under 1nm.
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We investigate the modulation of the localized surface plasmon resonance (LSPR) of a gold nanorod (AuNR) using a GeSbTe film as an active medium. We demonstrate high-contrast switching of LSPR in an AuNR/GST/Au thin film sandwich structure upon phase change. To go beyond this single-particle switching functionality, we consider a plasmon particle system interacting with a phase-change material (PCM) to discuss the possibility of parallel processing devices with memory functionality, exploiting the plasticity and threshold behavior that are inherent characteristics of PCMs. We demonstrate that the temporal and spatial evolution of a plasmon-PCM array system can be equivalent to a cellular automata algorithm.
We have investigated relationship between immersion topcoats and water, and between topcoats and ArF resist films for the use in ArF immersion lithography from the stand point of the work of adhesion characteristics. We evaluated surface free energy of topcoat films and resist films each from the contact angle measurement. From values of measured free energy, we obtained work of adhesion between topcoats and water, and between topcoats and resist films. In addition, we calculated an interfacial free energy between topcoats and resist films, which is related to the interface stability. As a result of evaluation of the interfacial free energy of four different kinds of topcoats, the topcoat which has lower surface free energy was found to have lower work of adhesion between topcoat and water, and lower interfacial free energy between a topcoat and a resist. These results indicate that the topcoat which has lower surface free energy has more less interaction between water and topcoat and stabile interface between a topcoat and a resist film.
This paper examines improvement in post-etching gate critical dimension (CD) uniformity by post exposure bake (PEB) temperature control. Although intra-wafer and inter-wafer resist CD uniformity is improved by PEB temperature optimization, intra-wafer gate CD uniformity after etching could not be improved due to etcher-attributed factors. To improve these factors, we carried out two-step optimization that combines lithography CD optimization with etching CD optimization. By using this method, the optimization strategy can clarify the targets of optimization in each step. PEB temperature optimization was performed by two step optimization in which etcher-attributed CD variations were canceled out, leading to 66% improvement of gate etching CD uniformity successfully. Without any changes in modification parameter, this PEB temperature optimization proved to be applicable to several reticle patterns with different pattern density. Moreover, this optimization method proved the applicability to the gate process for a 55nm node logic device for the duration of five months without modification. The result proved its long-term stability and practicality.
