Yukinori Morita

National Institute of Advanced Industrial Science and Technology

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Shinji Migita

National Institute of Advanced Industrial Science and Technology

174

Hiroyuki Ota

National Institute of Advanced Industrial Science and Technology

167

Wataru Mizubayashi

National Institute of Advanced Industrial Science and Technology

121

Meishoku Masahara

National Institute of Advanced Industrial Science and Technology

119

Takashi Matsukawa

National Institute of Advanced Industrial Science and Technology

S. O’uchi

National Institute of Advanced Industrial Science and Technology

Yongxun Liu

Shenzhen University

Takahiro Mori

National Institute of Advanced Industrial Science and Technology

Kazuhiko Endo

Health Sciences University of Hokkaido

Koichi Fukuda

National Institute of Advanced Industrial Science and Technology

Cooperative Institutions

National Institute of Advanced Industrial Science and Technology

115

The University of Tokyo

Kyoto University

Tohoku University

Osaka University

Japan Science and Technology Agency

University of Tsukuba

Tokyo Institute of Technology

Toshiba (Japan)

National Institute for Materials Science

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Novel Device Architecture Proposal of Source Junctionless Tunneling Field-Effect Transistor (SJL-TFET)

Extended Abstracts of the 2020 International Conference on Solid State Devices and Materials (2014)

Y. Kondo Masakazu Goto Yukinori Morita Takahiro Mori Shinji Migita

10.7567/ssdm.2014.j-1-2

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Citations (2)

Development of Bio-MEMS Device for Cell Cluster Patterning by Using Dielectrophoresis Method

S Murakami Yukinori Morita Eiji NAKAMACHI

Recently, the investigation of cell-activation and tissue regeneration process has shown the great progress in the biomedical and biomechanical research fields. In this study fabricated Biomedical-Micro Electric Mechanical System (Bio-MEMS) to examine accurately the cell activation by introducing the cell patterning assignment technique, which consists of the photolithograph method to generate the MEMS device and the cell patterning technique by using the dielectrophoresis (DEP) method. In the development of Bio-MEMS devices for cell culture and micro-bioreactor system, unresolved subjects, 1) the fundamental mechanism of cell activation, 2) the flow control of culture medium 3) the accurate cell pattern technique and 4) the implementation of positive DEP methods, are remained. In this study, we fabricate 2-D patterns of point by using the DEP method introducing the positive effects and the trap method by employing the gravity effect and the adhesion technique, to reveal the fundamental mechanism of cell activations, such as the nerve cell axon extension. We succeed to establish the cell patterning technique by using a novel electrode design technique, such as 2-D patterns of point. The results is shown that our novel approach using comprehensive designed electrodes is superior to cell patterning. Therefore, our device able to produce neural network consists of a large number of cells.

Dielectrophoresis

10.1115/imece2013-64295

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Variability Characterization in Isoelectronic-Trap-Assisted TFETs

The Japan Society of Applied Physics (2016)

Takahiro Mori Shinji Migita Koichi Fukuda Yukinori Morita Wataru Mizubayashi

Characterization

Trap (plumbing)

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Effects of Interfacial Layers Formed by Plasma Oxidation and Nitridation on HfO₂/Ge-MIS Properties

ECS Transactions (2006)

Tatsuro Maeda Yukinori Morita Masayasu nisizawa Shinichi Takagi

We report successful fabrication of oxide and nitride interfacial layers on Ge substrates by means of low-temperature plasma processing on Ge substrate. A transmission electron microscope observation revealed that the obtained interfacial layers are atomically smooth. The interface trap density (D it ) was measured for Au/HfO 2 /Ge metal/insulator/ semiconductor (MIS) structures with oxide and nitride interfacial layers by the ac conductance method. It is found that a minimum D it value of 1.0×10 11 cm -2 •eV -1 is obtained for the oxide samples after forming gas annealing (FGA) at 400ºC. Significant improvements by FGA on the electrical properties of the samples with nitride interfacial layers, including the reduction of D it from 1.8×10 12 to 1.5×10 11 cm -2 •eV -1 , are also demonstrated.

10.1149/1.2355852

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Citations (7)

Ideal hydrogen termination of Si(001) surface by wet-chemical preparation

Applied Physics Letters (1995)

Yukinori Morita Hiroshi Tokumoto

A nearly ideal Si(001) surface was prepared by a wet-chemical method with a solution of HF:HCl=1:19 (pH<1). The surface was examined by scanning tunneling microscopy and was found to be covered by the uniform dihydride phase. Its successful preparation was the direct consequence of the following facts: The suppression of the (111) facet formation due to a low concentration of OH ions in the etchant solution and the stabilization of the surfaces structure due to the formation of the ordered steps.

Facet (psychology)

10.1063/1.114326

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Citations (93)

Microstructural Change in Hf 0.5 Zr 0.5 O 2 Ferroelectric Thin Films during Phase Transformation

The Japan Society of Applied Physics (2019)

Shinji Migita Hiroyuki Ota Yukinori Morita

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Heated ion implantation for high-performance and highly reliable silicon-on-insulator complementary metal–oxide–silicon fin field-effect transistors

Japanese Journal of Applied Physics (2015)

Wataru Mizubayashi Hiroshi Onoda Yoshiki Nakashima Yuki Ishikawa Takashi Matsukawa

We have investigated the impact of heated ion implantation (I/I) on the performance and reliability of silicon-on-insulator (SOI) complementary metal–oxide–silicon (CMOS) fin field-effect transistors (FinFETs). An implantation temperature equal to and higher than 400 °C is needed to maintain the crystallinity of the Si substrate during I/I within the experimental conditions of ion species, implantation energy, and ion dose in this study. By heated I/I at 500 °C, the 11-nm-thick SOI layer perfectly maintains the crystallinity even after I/I, and a defect-free crystal is obtained by activation annealing. It was clarified that the cap layer is essential for the suppression of the out-diffusion during heated I/I. Heated I/I on the source and drain improves the on-current–off-current (Ion–Ioff), threshold voltage (Vth) variability, and bias temperature instability (BTI) characteristics of nMOS and pMOS FinFETs as compared with those after room-temperature I/I.

Fin

10.7567/jjap.54.04da06

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Cryogenic operation of double-gate FinFET and demonstration of analog circuit at 4.2K

S. O’uchi Kazuhiko Endo Masaaki Maezawa Tadashi Nakagawa Hiroyuki Ota

Performance of a double-gate (DG) FinFET in the cryogenic environment is discussed based on measurements and simulation. It was found that the DG FinFET has an excellent immunity to the kink effect in the cryogenic environment. Our physics-based compact model reproduced the measured I-V characteristics. The successful demonstration of an opamp consisting of the DG FinFETs at 4.2 K is also presented.

Cryogenic temperature

Cryogenics

Double gate

10.1109/soi.2012.6404376

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Citations (6)

Si(111)−√3 × √3 R30°: Si mediated by hydrogen desorption

Surface Science (1993)

Yukinori Morita Kazushi Miki Hiroshi Tokumoto

Surface reconstruction

Redistribution

10.1016/0039-6028(93)90068-u

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Citations (19)

Fabrication of High-k Gate Insulator Films by Atomic Layer Deposition and Their Properties Influenced by Substrate Hydrophilicity

Journal of the Vacuum Society of Japan (2011)

Yukinori Morita Shinji Migita Wataru Mizubayashi Hiroyuki Ota

We examined the impact of surface chemical nature prior to atomic layer deposition (ALD) to the electrical properties of high-k gate stacks on Si substrates. We confirmed that poor electrical film quality in ALD-HfO2 fabricated on H-terminated surfaces is drastically improved by changing the surface species terminating topmost Si bonds to be hydrophilicized. Especially, the high-k gate stacks fabricated on the surfaces chemically controlled by “oxygen-termination” technique showed excellent interfacial electrical quality without creating thick interfacial SiO2 layer.

Deposition

10.3131/jvsj2.54.105

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