Christoph Baumhof

Hyperstone (Germany)

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F. Muller

Technical University of Munich

N. Vogiatzis

Alcatel Lucent (Germany)

Olivier Muller

Techniques of Informatics and Microelectronics for Integrated Systems Architecture

Matthias Steck

Hyperstone (Germany)

Jens Spinner

HTWG Hochschule Konstanz - Technik, Wirtschaft und Gestaltung

D. Reisis

National and Kapodistrian University of Athens

Steve Kwee

Hamburg University of Technology

J. Kernhof

Renesas Electronics (Japan)

Gerd Bohlender

Karlsruhe Institute of Technology

Peter Schramm

University Hospital Schleswig-Holstein

Cooperative Institutions

National Technical University of Athens

National and Kapodistrian University of Athens

Hyperstone (Germany)

Ellemedia Technologies (Greece)

Institut für Mikroelektronik Stuttgart

Technical University of Crete

HTWG Hochschule Konstanz - Technik, Wirtschaft und Gestaltung

University of Konstanz

Institute of Communication and Computer Systems

Inaccess (Greece)

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A new VLSI vector arithmetic coprocessor for the PC

Christoph Baumhof

A new vector arithmetic coprocessor MIM XPA3233 with integrated PCI bus interface has been developed in CMOS VLSI technology. The chip performs dot products of vectors with components of the IEEE DOUBLE data format to full accuracy or with only one final rounding. Details on the realisation of the multiplication, accumulation and carry resolution processes are discussed. Performance data and some details about the actual VLSI realisation are presented. Software support for the coprocessor is available in the programming languages PASCAL-XSC and C-XSC or from a special C subroutine library. Programming examples are shown using PASCAL-XSC and C.< >

Coprocessor

Pascal (unit)

Subroutine

Realisation

10.1109/arith.1995.465356

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Citations (13)

A CMOS Floating-Point Processing Chip for Verified Exact Vector Arithmetic

J. Kernhof Christoph Baumhof B. Höfflinger Ulrich Kulisch Steve Kwee

A 33 MHz CMOS floating-point coprocessor which computes the vector scalar product without rounding errors has been designed. Using a floating-point algorithm for verified numerical computation, an ultra-high accuracy for double-precision operations is achieved with a 4k-bit fixed-point accumulator. This new type of accumulation is composed of a dual-port RAM and a fast carry acceleration logic. A peak performance of 15 MFLOPs in scalar product operations has been attained by the use of parallel operations. The 45k gate chip has been fabricated with the semicustom GATE FOREST [1].

Dot product

Rounding

Floating-point unit

Coprocessor

Double-precision floating-point format

FLOPS

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Citations (7)

A novel 32 bit RISC architecture unifying RISC and DSP

IEEE International Conference on Acoustics Speech and Signal Processing (2002)

Christoph Baumhof F. Muller Olivier Muller M. Shlett

A novel 32 bit RISC architecture is presented which is the basis of a powerful general purpose microprocessor and in parallel a 16/32 bit fixed point DSP processor. This unifying of RISC and DSP was not achieved by simply using a microprocessor and DSP core, but a new concept for the implementation of DSP processors has been developed. With the architecture presented, it is proven that a DSP processor can be implemented by strictly using the RISC design philosophy. Besides providing basic 16 bit fixed point functionality, the architecture implements a set of DSP instructions that support an efficient mapping of common DSP algorithms to the processor.

Microprocessor

Texas Instruments DaVinci

32-bit

16-bit

Addressing mode

Microarchitecture

10.1109/icassp.1997.599836

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Citations (1)

Telecommunication Systems (2003)

‪Theofanis Orphanoudakis‬Stylianos Perissakis Kostas Pramataris Nikos Nikolaou N. Zervos

Provisioning

10.1023/a:1024442011132

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Citations (5)

A Digitally Programmable On-Chip RC-Oscillator in 0.25μm CMOS Logic Process

1993 IEEE International Symposium on Circuits and Systems (2005)

C. Ghidini J.G. Aranda D. Gerna K. Kelliher Christoph Baumhof

The design of a process compensated RC on-chip oscillator with internally generated current and voltage references is presented. The oscillator provides a selectable clock (30 MHz to 36 MHz) with digital trimming to minimize process variations (/spl plusmn/45% in resistance value and /spl plusmn/15% in capacitance value). After fine-tuning, the oscillator guarantees less than /spl plusmn/2% frequency variation from 0 to 80 degrees, when operating down to 2 V. A 5-bit programmable fringe capacitor array was custom designed and modeled to overcome the lack of reliable capacitance devices in logic processes. The module was implemented in a 0.25 /spl mu/m CMOS logic process, occupies an area of 444/spl times/280 /spl mu/m/sup 2/ (bandgap excluded) and requires no external reference or components.

Trimming

Digitally controlled oscillator

10.1109/iscas.2005.1464609

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Citations (14)

A BCH decoding architecture with mixed parallelization degrees for flash controller applications

Jens Spinner Jürgen Freudenberger Christoph Baumhof A. Mehnert Richard Willems

Error correction coding (ECC) has become one of the most important tasks of flash memory controllers. The gate count of ECC hardware is taking up a significant share of the overall SOC logic. Scaling ECC strength to growing error correction requirements has become increasingly difficult when considering cost and area limitations. In this work, a new BCH decoding architecture is presented that combines different parallelization degrees for the Berlekamp-Massey algorithm and the Chien search. This approach significantly reduces the number of required multipliers. Nevertheless, the average decoding speed is equal to that of a fully parallel implementation.

BCH code

10.1109/socc.2013.6749671

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Citations (2)

A VLSI vector arithmetic coprocessor for the PCs.

rita_ (1996)

Christoph Baumhof Gerd Bohlender

Coprocessor

Source

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Citations (0)