Test and verification are essential parts during a product's development cycle. Simulation and emulation are well known techniques to test and verify the functionality of a design-under-test (DUT) before its tape-out. However, there are additional issues like peak power consumption and supply voltage drops, which can compromise a hardware's functionality. These issues are only partly covered by nowadays functional hardware emulation test and verification approaches. This paper presents a comprehensive emulation methodology. It combines functional hardware emulation with model-based performance, power, and supply voltage analysis techniques. The DUT, which has to be available in a hardware description language, is integrated into a FPGA along with designated analysis units. These analysis units implement models of the DUT's performance, power consumption, and supply voltage behavior. The presented emulation methodology allows a designer to test designs in such a way that the cycle accurate results are taken online, in real-time, and verify both functional and performance behavior, as well as power consumption and supply voltage levels. The proposed comprehensive emulation methodology is used, as an example of application, to verify the design of a LEON3 multi-core processor system as well as a RF-powered contacatless smart card. The depicted results demonstrate that this emulation approach is suitable to detect functional misbehavior caused by power and supply voltage hazards and how they influence the performance of the system.
During recent years the increasing introduction of system functionality into integrated devices resulted into several new problems for chip designers. First, high system-on-chip complexity combined with increased clock frequencies leads to power budget and thermal issues. Second, small semiconductor process structures are more sensitive to faults resulting from logic degradation and external radiation sources. Early testing and evaluation of hardware and software implementations have been enabled in the last years using hardware-accelerated emulation techniques. Such implementations rely on functional models of the target system, generated using specialized benchmark suites. These have been designed to accurately resemble typical application scenarios of the target implementation. Unfortunately, power and fault injection emulation accuracy is depending on a good coverage of the system's logic, which is not guaranteed by typical benchmarks. Therefore, this paper proposes an exhaustive hardware accelerated methodology for the evaluation of such applications and generation of accurate emulation models. The behavior of standard benchmarks are investigated using an open available system-on-chip platform based case study.
The rising demand for Near Field Communication (NFC), which uses the RFID technology, drives the market to deliver up to 500 million devices in 2014. The applications for RFID spread from simple identification to wireless gateways for embedded systems. The integration of this RFID-Reader in smart phones are an example for mobile RFID-Systems. Unfortunately, this integration leads to a decreased smart phones battery life, through the increased power consumption. To decrease this consumption, power management techniques like magnetic field strength scaling have been proposed. This technique adapts the amount of transferred power to the requirements of the transponder. This technique does not consider multiple transponders in transmission range. Therefore, this paper proposes an adapted version of the reader's transponder-detection process using magnetic field strength scaling to reduce the reader's battery drain. The adapted version has been implemented by two novel methods. These two methods have been experimentally verified by a case study. The potential of needing less battery drain is evaluated and compared to different possible implementations. In this case study, the battery drain needed by the RFID-Reader can be reduced by up to 34% using magnetic field strength scaling for multiple transponders.
More and more mobile devices are being produced to fulfill increasing consumer demand for immediate entertainment, instant information, and communications anywhere at any time. Mobile and wearable devices are designed to have the longest possible active-on and standby times and lowest weight and smallest size. Size and weight can be significantly decreased by using energy-efficient design methodologies. System-on-chip (SOC) and system-in-package (SIP) emerged as key technologies for developing wearable devices. The design of energy-aware gadgets includes not only hardware, but also software techniques. In this paper a single-chip multimedia system is reviewed for use within wearable devices. The presented results are derived from studying the behavior of an MP3 player produced by austriamicrosystems.
