Qinke Wang

Southwest University of Science and Technology

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Andrew B. Kahng

University of California, San Diego

Jianlin Ma

Southwest Jiaotong University

Yukun Ji

China University of Mining and Technology

Zhongbo Hu

University of Chinese Academy of Sciences

Ion Măndoiu

University of Connecticut

Sherief Reda

John Brown University

Wenlong Chen

Lanzhou University of Technology

Chung‐Kuan Cheng

University of California, San Diego

Shuai Cao

Southeast University

Hongyu Chen

Shanghai Ninth People's Hospital

Cooperative Institutions

Southwest Jiaotong University

University of California, San Diego

Chinese Academy of Sciences

University of California, Los Angeles

China University of Mining and Technology

Ministry of Agriculture and Rural Affairs

Chinese Academy of Tropical Agricultural Sciences

University of California, Berkeley

University of Connecticut

PowerChina (China)

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Plant–soil feedbacks under resource limitation may not contribute to the invasion by annual Asteraceae plants

Oecologia (2020)

Wang Ya Guangyan Ni Yuping Hou Qinke Wang Qiaoqiao Huang

10.1007/s00442-020-04756-z

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Citations (7)

Lens Aberration Aware Timing-Driven Placement

Andrew B. Kahng Chul‐Hong Park Puneet Sharma Qinke Wang

Process variations due to lens aberrations are to a large extent systematic, and can be modeled for purposes of analyses and optimizations in the design phase. Traditionally, variations induced by lens aberrations have been considered random due to their small extent. However, as process margins reduce, and as improvements in reticle enhancement techniques control variations due to other sources with increased efficacy, lens aberration-induced variations gain importance. For example, our experiments indicate that lens aberration can result in upto 8% variation in cell delay. In this paper, we propose an aberration-aware timing-driven analytical placement approach that accounts for aberration-induced variations during placement. Our approach minimizes the design's cycle time and prevents hold-time violations under systematic aberration-induced variations. On average, the proposed placement technique reduces cycle time by∼5% at the cost of∼2% increase in wirelength.

Reticle

10.1109/date.2006.243803

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Citations (11)

Vertical bearing performance of a concrete-filled steel tubular single pile and pile group in sand-rock composite ground

Applied Ocean Research (2024)

Zhongbo Hu Shishu Zhang Qinke Wang Guoliang Zhao Cheng Zhan

10.1016/j.apor.2024.104371

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Timing-driven Steiner trees are (practically) free

Charles J. Alpert Andrew B. Kahng C. N. Sze Qinke Wang

Traditionally, rectilinear Steiner minimum trees (RSMT) are widely used for routing estimation in design optimizations like floorplanning and physical synthesis. Since it optimizes wirelength, an RSMT may take a non-direct route to a sink, which may give the designer an unnecessarily pessimistic view of the delay to the sink. Previous works have addressed this issue through performance-driven constructions, minimum Steiner arborescence, and critical sink based Steiner constructions. Physical synthesis and routing flows have been reticent to adapt universal timing-driven Steiner constructions out of fear that they are too expensive (in terms of routing resource and capacitance). This paper studies several different performance-driven Steiner tree constructions in order to show which ones have superior performance. A key result is that they add at most 2%-4% extra capacitance, and are thus a promising avenue for today's increasingly aggressive performance-driven P&R flows. We demonstrate using a production P&R flow that timing-driven Steiner topologies can be easily embedded into an incremental routing subflow to obtain significantly improved timing (3.6% and 5.1% improvements in cycle time for two industry testcases) at practically no cost of wirelength or routability.

Steiner tree problem

10.1145/1146909.1147012

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Citations (28)

Parametric Analysis of Slope Stability Improved with Soil-cement Using Numerical Method

Journal of Applied Science and Engineering (2019)

Yanxin Yang Qinke Wang Jianlin Ma Fengjuan Huang

ABSTRACT Many stabilization methods exist to improve slope stability. One of them is using soil-cement improvement technique. The method used the soil-cement slices constructed on the surface of a slope based upon a certain spacing across the slope with a shear key embedded deeper in slope. Parametric analysis of slope improved with soil-cement-based method was conducted using Shear Strength Reduction Finite Element Method (SSR-FEM). An ideal slope was used to analyze the variation of factors of safety. The factors of safety of the slopes treated with soil-cement-based stabilization were improved comparing those without treatment.Various factors of the slopes that controlled the factor of safety were studied in the parametric analysis.The increases of the internal friction angle, the cohesion of the soil of the slope, the length of the short edge and the depth of embedment will improve the factor of safety. Moreover, the analysis results show that the internal friction angle of soil were correlated with the factor of safety in the exponential relationship, and the cohesion of soil, the length of the short edge and the depth of embedment were correlated with the factor of safety in the linear relationship. The value of interface strength reduction coefficient was correlated with the factor of safety in the logarithmic relationship. However, the interface strength reduction coefficient has less effects on the factor of safety comparing to the other factors. The factor of safety varied with the spacing of slice,and an optimum spacing could be determined based on the distribution of factor of safety. The soil arching effects were also explored and found they improved the factor of safety. Two case histories of slopes were analyzed and the improved factor of safety was proved for each case.

Embedment

Cohesion (chemistry)

Safety factor

Factor of safety

Strength reduction

Friction angle

Shear Strength

10.6180/jase.201909_22(3).0006

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Effects of soil nutrients on reproductive traits of invasive and native annual Asteraceae plants

Biodiversity Science (2021)

Wang Ya Weiqian Wang Qinke Wang Xiaoxia Li Yan Liu

状的影响, 并进一步研究养分添加是否更能促进入侵植物的繁殖能力, 我们设置了低、高两个养分水平, 通过同质园实验比较了不同土壤养分对假臭草(Praxelis clematidea)、胜红蓟(Ageratum conyzoides)、三叶鬼针草(Bidens pilosa) 3种菊科一年生入侵种和夜香牛(Vernonia cinerea)、一点红(Emilia sonchifolia)、墨旱莲(Eclipta prostrata) 3种本地种繁殖性状的影响。研究结果显示, 养分添加提高了6种菊科植物的开花株高、株高、地上生物量、单粒种子重量、总花序数、每花序种子数、总种子数量、总种子重量, 并使开花时间提前、花期延长。养分添加对入侵种的开花株高和单粒种子重量的提高幅度要比本地种更显著。相对于部分本地植物(

Soil nutrients

Native plant

10.17520/biods.2020212

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Citations (4)

Architecture and details of a high quality, large-scale analytical placer

Andrew B. Kahng Sherief Reda Qinke Wang

Modern design requirements have brought additional complexities to netlists and layouts. Millions of components, whitespace resources, and fixed/movable blocks are just a few to mention in the list of complexities. With these complexities in mind, placers are faced with the burden of finding an arrangement of placeable objects under strict wirelength, timing, and power constraints. In this paper we describe the architecture and novel details of our high quality, large-scale analytical placer. The performance of our placer has been recently recognized in the recent ISPD-2005 placement contest, and in this paper we disclose many of the technical details that we believe are key factors to its performance. We describe (i) a new clustering architecture, (ii) a dynamically adaptive analytical solver, and (iii) better legalization schemes and novel detailed placement methods. We also provide extensive experimental results on a number of benchmark sets. On average, our results are better than the best published results by 3%, 14%, and 6% for the IBM ISPD '04, ICCAD '04, and ISPD '05 benchmark sets respectively. One of the goals of this paper is to also provide enough details to enable possible future replication of our methods.

Benchmark (surveying)

IBM

Solver

10.5555/1129601.1129727

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Citations (86)

The Y-architecture for on-chip interconnect: analysis and methodology

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486) (2003)

Hongyu Chen Chung‐Kuan Cheng A.B. Kahng Ion Măndoiu Qinke Wang

The Y-architecture for on-chip interconnect is based on pervasive use of 0-, 120-, and 240-degree oriented semi-global and global wiring. Its use of three uniform directions exploits on-chip routing resources more efficiently than traditional Manhattan wiring architecture. This paper gives in-depth analysis of deployment issues associated with the Y-architecture. Our contributions are as follows: (1) We analyze communication capability (throughput of meshes) for different interconnect architectures using a multi-commodity flow approach and a Rentian communication model. Throughput of the Y-architecture is largely improved compared to the Manhattan architecture, and is close to the throughput of the X-architecture. (2) We propose a symmetrical Y clock tree structure with better total wire length compared to both H and X clock tree structures, and better path length compared to the H tree. (3) We discuss power distribution under the Y-architecture, and give analytical and SPICE simulation results showing that the power network in Y-architecture can achieve 8.5% less IR drop than an equally-resourced power network in Manhattan architecture. (4) We propose the use of via tunnels and banks of via tunnels as a technique for improving routability for Manhattan and Y-architectures.

Tree (set theory)

Space-based architecture

Electronic design automation

10.1109/iccad.2003.159664

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Citations (4)

Field test on uplift bearing characteristics of transmission tower foundation in mountainous areas of western China

Environmental Earth Sciences (2021)

Qinke Wang Jianlin Ma Mengting Wang Yukun Ji

Transmission tower

Foundation (evidence)

10.1007/s12665-021-09851-9

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Citations (6)

Supply voltage degradation aware analytical placement

International Conference on Computer Design (2006)

Andrew B. Kahng Bao Liu Qinke Wang

Increasingly significant power/ground supply voltage degradation in nanometer VLSI designs leads to system performance degradation and even malfunction. Existing techniques focus on design and optimization of power/ground supply networks. In this paper, we propose supply voltage degradation aware placement, e.g., to reduce maximum supply voltage degradation by relocation of supply current sources. We represent supply voltage degradation at a P/G node as a function of supply currents and effective impedances (i.e., effective resistances in DC analysis) in a P/G network, and integrate supply voltage degradation in an analytical placement objective. For scalability and efficiency improvement, we apply random-walk, graph contraction and interpolation techniques to obtain effective resistances. Our experimental results show an average 20.9% improvement of worst-case voltage degradation and 11.7% improvement of average voltage degradation with only 4.3% wirelength increase.

Degradation

10.1109/iccd.2005.101

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Citations (16)