VHSIC hardware description language (VHDL) is compared to three other well-known hardware description languages: Verilog (from Cadence Design Systems, now public), UDL/1 (new Japanese standards,) and M (from Mentor Graphics). This comparative study parallels the fundamental concepts of these languages and highlights the different design processes and methodologies they require. VHDL is a general-purpose modeling language, whereas Verilog, UDL/I and M are more dedicated to IC modeling. The predefined environment of VHDL compares poorly to the implicit IC environment of other languages. >

Verilog

Electronic circuit design

10.5555/159754.161862

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Citations (6)

Non-reversible VHDL source-source encryption

European Design Automation Conference (1994)

Kevin O’Brien Serge Maginot

once-off basis in order to combine their two models on a chip. A typical model consists of a large number of hierarchical entity-architecture pairs that interface with a set of packages. These packages may be used for describing the environment surrounding the model such as a library of units representing the underlying technology or some common functions, as well as standard packages such as std_logic_1164. The partner supplying this model would like the recipient to be able to simulate it but not to be able to use the information supplied elsewhere. In this paper, we present KRYPTON, a nonreversible, VHDL source to source encryption tool. By generating non-reversible encrypted VHDL we do away with the classic problems of encryption tools such as portability and the risk of decryption. KRYPTON has been successfully tested on industrial models containing over 100 VHDL units

Software portability

10.5555/198174.198308

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Citations (12)

Predefined Attribute ’Ascending

Kluwer international series in engineering and computer science (1993)

Jean-Michel Bergé Alain Fonkoua Serge Maginot Jacques Rouillard

10.1007/978-1-4615-3246-0_14

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Predefined Attribute Driving_Value (and ’Driving)

Kluwer international series in engineering and computer science (1993)

Jean-Michel Bergé Alain Fonkoua Serge Maginot Jacques Rouillard

Port (circuit theory)

Value (mathematics)

10.1007/978-1-4615-3246-0_13

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Towards maximising the use of structural VHDL for synthesis

European Design Automation Conference (1996)

K. O'Brien A. Andrew Roobert Serge Maginot

In this paper we show that by performing some VHDL elaboration transformations before synthesis we can extend the synthesis subset to include complex structural and hierarchical statements. This in turn means that: design, debug and simulation times are reduced; designs are more accessible (readable, modifiable, portable, reusable); design prototyping can be speeded up. All of this can be achieved without the need to modify existing synthesis tools.

High-Level Synthesis

10.5555/252471.252558

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Citations (2)