Georgios Goumas

National Technical University of Athens

Author Statistics

Papers

Citation

H-Index

i-10 index

Research Trends

Author Order

Document Type

Co-Authors

Nectarios Koziris

National Technical University of Athens

Konstantinos Nikas

National Technical University of Athens

Christina Giannoula

Vector Institute

ΝΠ

Νικέλα Παπαδοπούλου

University of Glasgow

Vasileios Karakasis

CSCS - Swiss National Supercomputing Centre

Kornilios Kourtis

IBM (United States)

Athena Elafrou

National Technical University of Athens

Juan Gómez-Luna

ETH Zurich

Vasileios Karakostas

National and Kapodistrian University of Athens

Dimitrios Siakavaras

National Technical University of Athens

Cooperative Institutions

National Technical University of Athens

National and Kapodistrian University of Athens

Institute of Communication and Computer Systems

ETH Zurich

Carnegie Mellon University

Georgia Institute of Technology

Athena Research and Innovation Center In Information Communication & Knowledge Technologies

Universitat Politècnica de Catalunya

Foundation for Research and Technology Hellas

University of Edinburgh

Author Statistics

Papers

Citation

H-Index

i-10 index

Research Field

SmartPQ: An Adaptive Concurrent Priority Queue for NUMA Architectures

arXiv (Cornell University) (2024)

Christina Giannoula Foteini Strati Dimitrios Siakavaras Georgios Goumas Nectarios Koziris

Concurrent priority queues are widely used in important workloads, such as graph applications and discrete event simulations. However, designing scalable concurrent priority queues for NUMA architectures is challenging. Even though several NUMA-oblivious implementations can scale up to a high number of threads, exploiting the potential parallelism of insert operation, NUMA-oblivious implementations scale poorly in deleteMin-dominated workloads. This is because all threads compete for accessing the same memory locations, i.e., the highest-priority element of the queue, thus incurring excessive cache coherence traffic and non-uniform memory accesses between nodes of a NUMA system. In such scenarios, NUMA-aware implementations are typically used to improve system performance on a NUMA system. In this work, we propose an adaptive priority queue, called SmartPQ. SmartPQ tunes itself by switching between a NUMA-oblivious and a NUMA-aware algorithmic mode to achieve high performance under all various contention scenarios. SmartPQ has two key components. First, it is built on top of NUMA Node Delegation (Nuddle), a generic low-overhead technique to construct efficient NUMA-aware data structures using any arbitrary concurrent NUMA-oblivious implementation as its backbone. Second, SmartPQ integrates a lightweight decision making mechanism to decide when to switch between NUMA-oblivious and NUMA-aware algorithmic modes. Our evaluation shows that, in NUMA systems, SmartPQ performs best in all various contention scenarios with 87.9% success rate, and dynamically adapts between NUMA-aware and NUMA-oblivious algorithmic mode, with negligible performance overheads. SmartPQ improves performance by 1.87x on average over SprayList, the state-of-theart NUMA-oblivious priority queue.

Priority inheritance

10.48550/arxiv.2406.06900

Cite

Citations (0)

CIRANO: An Integrated Programming Environment for Multi-tier Cloud Based Applications

Procedia Computer Science (2015)

G. Fylaktopoulos Georgios Goumas M. Skolarikis Aris Sotiropoulos Dimitrios Athanasiadis

This paper describes the CIRANO platform, a cloud Integrated Development Environments (IDE) that substantially supports Model Driven Development (MDD) and team collaboration, in order to facilitate the development of cloud–based applications. The paper presents the state of the art in the field and discusses the technical details of CIRANO architecture and its modular implementation. The main features of the proposed platform are presented as a case study application concerning the update and porting of an existing collaboration system, called Comidor. The paper discusses the findings in comparison with existing tools and proposes extensions of the platform as future work.

10.1016/j.procs.2015.09.222

Cite

Citations (5)

Open-Source SpMV Multiplication Hardware Accelerator for FPGA-Based HPC Systems

Lecture notes in computer science (2024)

Panagiotis Mpakos Ioanna Tasou Chloe Alverti Panagiotis Miliadis Pavlos Malakonakis

Kernel (algebra)

Double-precision floating-point format

10.1007/978-3-031-55673-9_2

Cite

Citations (0)

Feature-based SpMV Performance Analysis on Contemporary Devices

2022 IEEE International Parallel and Distributed Processing Symposium (IPDPS) (2023)

Panagiotis Mpakos Dimitrios Galanopoulos Petros Anastasiadis Νικέλα Παπαδοπούλου Nectarios Koziris

The SpMV kernel is characterized by high performance variation per input matrix and computing platform. While GPUs were considered State-of-the-Art for SpMV, with the emergence of advanced multicore CPUs and low-power FPGA accelerators, we need to revisit its performance and energy efficiency. This paper provides a high-level SpMV performance analysis based on structural features of matrices related to common bottlenecks of memory-bandwidth intensity, low ILP, load imbalance and memory latency overheads. Towards this, we create a wide artificial matrix dataset that spans these features and study the performance of different storage formats in nine modern HPC platforms; five CPUs, three GPUs and an FPGA. After validating our proposed methodology using real-world matrices, we analyze our extensive experimental results and draw key insights on the competitiveness of different target architectures for SpMV and the impact of each feature/bottleneck on its performance.

Kernel (algebra)

Memory bandwidth

Performance Improvement

Multi-core processor

10.1109/ipdps54959.2023.00072

Cite

Citations (2)

Performance Prediction of NUMA Placement: A Machine-Learning Approach

Fanourios Arapidis Vasileios Karakostas Νικέλα Παπαδοπούλου Konstantinos Nikas Georgios Goumas

In this paper we present a machine-learning approach to predict the impact on performance of core and memory placement in non-uniform memory access (NUMA) systems. The impact on performance depends on the architecture and the application's characteristics. We focus our study on features that can be easily extracted with hardware performance counters that are found in commodity off-the-self systems. We run various single-threaded benchmarks from Spec2006 and Parsec under different placement scenarios, and we use this benchmarking data to train multiple regression models that could serve as performance predictors. Our experimental results show notable accuracy in predicting the impact on performance with relatively simple prediction models.

Benchmarking

Parsec

Performance Prediction

10.1109/cloudcom2018.2018.00064

Cite

Citations (1)

Understanding the Performance of Sparse Matrix-Vector Multiplication

Georgios Goumas Kornilios Kourtis Nikos Anastopoulos Vasileios Karakasis Nectarios Koziris

In this paper we revisit the performance issues of the widely used sparse matrix-vector multiplication (SpMxV) kernel on modern microarchitectures. Previous scientific work reports a number of different factors that may significantly reduce performance. However, the interaction of these factors with the underlying architectural characteristics is not clearly understood, a fact that may lead to misguided and thus unsuccessful attempts for optimization. In order to gain an insight on the details of SpMxV performance, we conduct a suite of experiments on a rich set of matrices for three different commodity hardware platforms. Based on our experiments we extract useful conclusions that can serve as guidelines for the subsequent optimization process of the kernel.

Kernel (algebra)

Matrix (chemical analysis)

10.1109/pdp.2008.41

Cite

Citations (72)

An efficient and fair scheduling policy for multiprocessor platforms

2022 IEEE International Symposium on Circuits and Systems (ISCAS) (2017)

Theodoros Marinakis Alexandros-Herodotos Haritatos Konstantinos Nikas Georgios Goumas Iraklis Anagnostopoulos

Scheduling is a decision-making process that deals with the assignment of resources to tasks over given periods, aiming to optimize one or more objectives. Responsible for efficient distribution of the CPU time among the processes, scheduler has become an essential part of computer systems. While applications run on neighboring cores of a many-core system, they compete with each other for the shared resources (cache, memory etc.). This contention can result in great performance degradation for the applications that are concurrently executed. For this reason, treating the cores of a many-core systems as isolated and independent units is a very optimistic abstraction and can cause great problems to the objectives a scheduler tries to optimize. This paper presents a scheduler that focuses on improving the system's fairness by deciding the group of applications that will be executed together based on the progress they have performed. Results shows that the proposed scheduler achieves on average 86% fairness improvement compared to two state-of-art schedulers.

Multi-core processor

Abstraction

10.1109/iscas.2017.8050758

Cite

Citations (4)

Message-passing code generation for non-rectangular tiling transformations

Parallel Computing (2006)

Georgios Goumas Nikolaos Drosinos Maria Athanasaki Nectarios Koziris

Code (set theory)

10.1016/j.parco.2006.07.003

Cite

Citations (9)

Towards Efficient Sparse Matrix Vector Multiplication on Real Processing-In-Memory Architectures

Christina Giannoula Ivan Fernandez Juan Gómez-Luna Nectarios Koziris Georgios Goumas

Several manufacturers have already started to commercialize near-bank Processing-In-Memory (PIM) architectures, after decades of research efforts. Near-bank PIM architectures place simple cores close to DRAM banks. Recent research demonstrates that they can yield significant performance and energy improvements in parallel applications by alleviating data access costs. Real PIM systems can provide high levels of parallelism, large aggregate memory bandwidth and low memory access latency, thereby being a good fit to accelerate the Sparse Matrix Vector Multiplication (SpMV) kernel. SpMV has been characterized as one of the most significant and thoroughly studied scientific computation kernels. It is primarily a memory-bound kernel with intensive memory accesses due its algorithmic nature, the compressed matrix format used, and the sparsity patterns of the input matrices given. This paper provides the first comprehensive analysis of SpMV on a real-world PIM architecture, and presents SparseP, the first SpMV library for real PIM architectures. We make two key contributions. First, we design efficient SpMV algorithms to accelerate the SpMV kernel in current and future PIM systems, while covering a wide variety of sparse matrices with diverse sparsity patterns. Second, we provide the first comprehensive analysis of SpMV on a real PIM architecture. Specifically, we conduct our rigorous experimental analysis of SpMV kernels in the UPMEM PIM system, the first publicly-available real-world PIM architecture. Our extensive evaluation provides new insights and recommendations for software designers and hardware architects to efficiently accelerate the SpMV kernel on real PIM systems. For more information about our thorough characterization on the SpMV PIM execution, results, insights and the open-source SparseP software package [21], we refer the reader to the full version of the paper [3, 4]. The SparseP software package is publicly and freely available at https://github.com/CMU-SAFARI/SparseP.

Kernel (algebra)

Memory bandwidth

10.1145/3489048.3522661

Cite

Citations (6)

An Extended Compression Format for the Optimization of Sparse Matrix-Vector Multiplication

IEEE Transactions on Parallel and Distributed Systems (2012)

Vasileios Karakasis Theodoros Gkountouvas Kornilios Kourtis Georgios Goumas Nectarios Koziris

Sparse matrix-vector multiplication (SpM × V) has been characterized as one of the most significant computational scientific kernels. The key algorithmic characteristic of the SpM × V kernel, that inhibits it from achieving high performance, is its very low flop:byte ratio. In this paper, we present a compressed storage format, called Compressed Sparse eXtended (CSX), that is able to detect and encode simultaneously multiple commonly encountered substructures inside a sparse matrix. Relying on aggressive compression techniques of the sparse matrix's indexing structure, CSX is able to considerably reduce the memory footprint of a sparse matrix, alleviating the pressure to the memory subsystem. In a diverse set of sparse matrices, CSX was able to provide a more than 40 percent average performance improvement over the standard CSR format in SMP architectures and surpassed 20 percent improvement in NUMA systems, significantly outperforming other CSR alternatives. Additionally, it was able to adapt successfully to the nonzero element structure of the considered matrices, exhibiting very stable performance. Finally, in the context of a "real-life" multiphysics simulation software, CSX accelerated the SpM × V component nearly 40 percent and the total solver time approximately 15 percent.

Matrix (chemical analysis)

Memory footprint

Kernel (algebra)

Solver

Matrix-free methods

10.1109/tpds.2012.290

Cite

Citations (47)