The success of the electrical fault isolation will assist in narrowing down to the most possible fault location with confidence, and thus increase the success rate in determining the failure mechanism during physical failure analysis. However, any form of recovery from the failure could result in inability to determine the root cause. For example, they are either the sample unable to send to FA since the device is passing, or unable to continue the fault isolation since recovery occurred during analysis. This technical paper will discuss on the investigation of recovery symptom in scan related failure for 55nm wafer technology devices. Through study and investigation, recovery avoidance is implemented during testing, and a new stress flow is identified to reactivate the failure mode. Thus, recoverable failure mechanism like passivation crack and metal defects are identified. The learning from the recovery characteristics also help to forecast possible failure mechanism based on the scan diagnostics and electrical fault isolation findings.
In this paper, a novel signal toggling technique in Electrical Optical Frequency Mapping/ Phase Mapping (EOFM/EOPM) and Electrical Optical probing (EOF) are performed to successfully localized the fault location and identify the physical defect promptly. A function square wave is asserted into the pin of interest, i.e. leakage pin or the function power pin, for EOFM and EOF purposes. This technique help to keep the cost of analysis down and improve the through-put time of the analysis as the technology of the wafer fab is shrinking. The initial technique evaluation was performed on the analog devices in advanced SOI-based circuits and the technique was successfully fan-in to digital CMOS device. Three case studies presented in this papers will demonstrate how the signal toggling in EOFM/EOF help to isolate to defect region.
Marginal failure is common in failure analysis in which the failure is dependant to voltage or timing. Instead of using conventional die top microprobing to isolate the failure location, Laser Assisted Device Alteration (LADA) together with modified test pattern to isolate the failure location by incorporating Atomic Force Probe (AFP) and Transmission Electron Microscopy (TEM) to determine the failure. In addition, LADA helps to provide information about the sensitive circuitry. This leads to design fix that will overcome the marginality of failure and thus improve overall yield.
This paper describes the use of Electrical Optical Frequency Mapping (EOFM) in amplitude and phase mode to binary search the broken scan cell and missing clock activities in scan-chain failure for Application-Specific Integrated Circuit (ASIC) die inside the sensor device. Due to the smaller size of the ASIC die at the bottom stack of the GCELL and the Evaluation Board (EVB) design which not favorable for higher Numerical Aperture (NA) objective lens analysis, it limits the use of FA techniques such as top side probing and Electro Optical Probing (EOP) using Solid Immersion Lens (SIL). Due to these limitation, the EOFM by using airgap lens from backside is evaluated to compliment the top side probing analysis or EOP using SIL. It is observed both the phase and amplitude mode in EOFM will assist in isolating the faulty scan cell and faulty scan clock module. Two case studies presented in this paper will demonstrate how the EOFM helps to isolate the broken scan cell and the missing clock module.
Scan design, being part of the most commonly practiced form of Design for Testability (DFT) has been developed to enable software based diagnosis for scan chain failures. Tessent Diagnosis helps to narrow down the reported failures to a suspected failing chain [1] - [5]. Unfortunately, scan chains can consist of hundreds to thousands of individual latches that can represent potential defect candidates and are typically distributed across the entire chip. Implementing global fault isolation techniques, which includes Photon Emission Microscopy (PEM) analysis, can lead to a collection of numerous anomalous emission spots. Cross mapping both the PEM results and the hundreds to thousands of individual scan cells to the CAD layout is both time-consuming and labor intensive. Moreover, selective cross mapping does not reveal the scan latches in chronological order, which is important for any scan chain analysis. One possible solution is to spatially map the scan latch list from the diagnosis file to the CAD layout to visualize the scan latch distribution quickly. This paper describes the use of this Scan Cell Visualizer through the use of case studies to demonstrate improved layout mapping efficiency and reduced overall failure analysis cycle time.
In this paper, combination of electrical fault isolation analysis of Soft-Defect Localization (SDL) technique and Electro-Optical Probing (EOP) technique for time delay issue are discussed. The integration of both techniques effectively pinpoints the Front-end-of-line (FEOL) or Back-end-of-line (BEOL) wafer process defects for time delay related issues. EOP will investigate the switching activities of the transistors and display its representative voltage level, but the effect of the delay will only be identified by analysts at the subsequent stage of logic or the fan-out driver from the failing signal node. By back tracing the circuitry with comparison to correlation unit, the EOP analysis is capable to isolate the delay at suspected signal routing but unable to determine the point of interest for physical analysis purposes. The estimated defect location can be further narrow down by using the SDL technique. The paper below describes the EOP characteristic of the transistors during time delay occurrence and the integration of SDL technique in FA flow for best physical defect region estimation.
As silicon technology scales down in size, front side fault localization for parametric failures in semiconductor devices has become more difficult. This is due to the increasing number of metallization layers. Hence, backside fault isolation techniques are employed. Challenges arise when the device packages are not designed for backside analysis. This is especially true for BGA (Ball Grid Array) packages. There are several approaches to perform backside analysis on BGA packages but some of them may be time and resources consuming. One such example is repackaging. This paper proposes a method to selectively thin the BGA package but yet preserves the electrical integrity and package spheres of interest for quick backside electrical analysis.
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