A novel mobility model for electrons in the Si-MOS inversion layer is proposed on the basis of two-dimensional degenerate electron gas physics. The mobility is found to be affected by Pauli's exclusion principle and the Fermi-Dirac distribution function. The universal relation between mobility and effective field strength in the normal direction can be consistently explained by the model, including its temperature dependence.< >
A 1/f noise model in MOS transistors has been developed by assuming both the mobility and density fluctuations in the channel. Using Si-gate MOS transistors with intentionally controlled interface properties, relations to 1/f noise of interface-state densities, gate voltages, process conditions and bias-temperature-stress-tests have been examined experimentally. These results are discussed by refering to the model. Process factors for 1/f noise reduction are also discussed.
The effect on device properties of the film deposited on a thermally oxidized silicon wafer has been investigated. Oxide thickness used is mainly about 6000Å. It is shown that bipolar transistor characteristics, i.e., current gain, junction reverse current, and 1/f noise are improved with increasing film thickness, except npn transistors at 2500Å of . The minority carrier lifetime in the bulk silicon is also shown to be increased with increasing film thickness, based upon the fact that surface recombination velocity is not appreciably affected. Lattice strain measurements by Newton ring or x‐ray rocking curve show that the lifetime increase is correlative with the reduction in the strain, which is a result of the thermal expansion rates difference. It is proposed that the lifetime be restored by the stress cancellation due to the combination of the and the on the silicon wafer. The film thickness dependence is also observed for films.
It is found that equivalent gate noise power for l/f noise in n-channel silicon-gate MOS transistors at near zero drain voltage at room temperature is empirically described by two noise terms, which vary as K_{1}(q/C_{ox}) (V_{G} -V_{T})/f and K_{2}(q/C_{ox})^{2}/f, where V_{G} is gate voltage, V T is threshold Voltage, and C ox is gate-oxide capacitance per unit area. Unification of carrier-density fluctuation (McWhorter's model)and mobility fluctuation (Hooge's model) can account for the experimental data. The comparison between the theory and experiment shows that the carrier fluctuation term K 2 is proportional to oxide-trap density at Fermi-level. The mobility fluctuation term K 1 is correlated to K 2 , being proportional to \radic K_{2} . The origin of this correlation is yet to be clarified.
Practical limitations in channel lengths for n-channel MOSFET'S under 5-V operation are discussed for conventional arsenic-drain, phosphorus-drain, phosphorus-arsenic double diffused drain (DDD), and lightly doped drain (LDD) structures. Process parameter dependence of device characteristics and optimal process conditions are also evaluated for each drain structure. It is clarified that the minimum usable channel length is about 0.7-µm, which is realized by the DDD and LDD devices. In these devices, the hot-carrier-induced device degradation is no longer a major restriction on minimum channel length, but the short-channel effect and the parasitic bipolar breakdown are dominant restrictions. The phosphorus drain with a shallow junction formed by rapid thermal annealing can expand the arsenic drain limitation.
A method to evaluate hot-carrier-induced NMOSFET degradation under dynamic stress is discussed, based on an empirical relation between device lifetime and substrate current in static stress. The device lifetime τ under dynamic stress is given by \tau = A.I_{sub,peak}^{-2.5}/R , where I_{sub,peak} is the peak value of pulsive substrate current and R is its duty ratio. The device lifetime experimentally obtained in an inverter circuit is in good agreement with the calculation results obtained from the proposed method. This method is useful to estimate device lifetime in actual circuit operational conditions.
Conditions to achieve shallow p+-junctions with low sheet resistance by using ion implantation and rapid thermal annealing (RTA), are presented. This work shows that (junction depth) × (sheet resistivity) \rho_{s}X_{j} has a smaller value with increasing implant dose and anneal temperature (boron solubility), and decreasing implant energy. However, the value is saturated for higher doses than 10 16 X j cm 2 , where X j is junction depth in micrometers, and anneal temperature should be lower than 1100°C, because of considerable boron diffusion even in 10-s RTA. \rho_{s}X_{j} = 18 Ω.µm is achieved by BF 2 + implantation with 5 × 10 15 -cm -2 dose at 30 keV and 1000°C RTA. The possibility of further improvement in \rho_{s}X_{j} value is discussed.
The structure, fabrication and electrical characteristics of a new one-transistor one-capacitor MOS memory cell for megabit DRAMs are presented. In the cell, a buried polysilicon electrode, refilled into a capacitor trench and connected to a transfer MOSFET electrode, serves to store the signal charge, while the heavily doped substrate of a p/p ++ epi wafer serves as the capacitor plate. Because of its inherent punchthrough-free nature and high immunity against alpha-particle soft errors, the cell is suitable for high density integration. A test element group of the cell was fabricated with 0.8um design rule yielding memory cell size of 8.8um 2 and storage capacitance of 35fF. Basic memory cell operation was demonstrated successfully, where the charge retention time of more than 2 sec was observed. The interference between the adjacent cells separated by 0.8um was confirmed to be negligible.
