Ria Bose

Maulana Abul Kalam Azad University of Technology, West Bengal

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Jitendra Nath Roy

Kazi Nazrul University

J. N. Roy

Indian Institute of Technology Kharagpur

Sabyasachi Sen

Jadavpur University

Madhumita Das Sarkar

Maulana Abul Kalam Azad University of Technology, West Bengal

Supratim Subhra Das

Aliah University

Pratip Chakraborty

Maulana Abul Kalam Azad University of Technology, West Bengal

Cooperative Institutions

Maulana Abul Kalam Azad University of Technology, West Bengal

Indian Institute of Technology Kharagpur

Jadavpur University

Corning (United States)

University at Albany, State University of New York

Aliah University

Centurion University of Technology and Management

Kazi Nazrul University

Central University of South Bihar

Laurentian University

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Three-Dimensional Channel Potential Model of a Triple Gate MOSFET based on Conformal Mapping Technique

IETE Technical Review (2021)

Ria Bose Jitendra Nath Roy

In this paper, an analytical channel potential model of an experimental nano-scaled triple gate MOSFET has been developed that is valid in the subthreshold regime. The potential model is derived by applying the Schwarz–Christoffel transformation method and conformal mapping techniques. The model is derived by superposing the influence of top gate on the potential barrier with the 2D potential solution, which is obtained by considering the presence of only two side gates. From that, the threshold voltage model of the device is also evaluated. To validate our model, the result has been compared with numerical simulation data from 3D TCAD Sentaurus that shows good accuracy for channel length (as short as 30 nm) considered for our device.

10.1080/02564602.2021.1903348

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Citations (1)

Performance Assessment of a Double Gate Work Function Engineered Doped Tunnel FET Based on 2D Surface Potential Model

2018 IEEE Electron Devices Kolkata Conference (EDKCON) (2018)

Ria Bose Jitendra Nath Roy

Two dimensional surface potential model of a work function engineered (WFE) doped double gate (DG) Tunnel Field Effect Transistor (TFET) structure is proposed and verified using TCAD Sentaurus device simulation. The overall electric field is estimated using the proposed model based on which device performance is analyzed. The proposed model is completely physics based and analytic and does not include any fitting parameters or iterative calculation. The proposed TFET structure employs gate which is made of two metals having different thicknesses and work functions acting as tunneling gate and control gate. Such configuration creates a n+ pocket enhancing carrier tunneling probability near source/channel junction. A comparative performance analysis is also performed between our proposed device and its normal double Gate (DG) counterpart.

Tunnel field-effect transistor

Double gate

Technology CAD

10.1109/edkcon.2018.8770436

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Analytical Modeling for Parasitics in a Triple Gate MOSFET Device

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) (2020)

Ria Bose Jitendra Nath Roy

In this paper, simple and analytical models are proposed for a experimental trigate FinFET device which provides a detailed understanding of the inbuilt parasitic resistance and capacitance of the device. The non planar device structures in nano scale regime usually experiences high parasitic resistances and capacitances due to having multiple gates, narrow fin width and narrow source/drain region width as well. A surface potential based charge model is also developed to determine parasitic capacitances. Our proposed model shows good agreement with 3D TCAD Sentaurus device simulation result. The model estimates a limit to scaling of parasitic source/drain resistance and also reveals that contact resistance dominates parasitic resistance of trigate FinFET device.

Parasitic extraction

Parasitic element

Parasitic capacitance

Fin

Contact resistance

10.1109/vlsidcs47293.2020.9179934

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Classical and quantum charge density model of nano scale doped DG MOSFETs below onset of strong inversion

Materials Research Express (2019)

Ria Bose J. N. Roy

Classical and quantum inversion charge density models are derived below threshold for a doped double-gate (DG) MOSFET. Since our charge density model includes a 2D analytical solution of channel potential considering the contribution of both mobile charge and doping concentration terms, the proposed models are also investigated slightly above threshold of the device having different channel lengths and validated by 2D TCAD (Technology Computer Aided Design) simulation. Quantum Confinement Effects are incorporated in quantum model by considering a 1D infinite rectangular well with a perturbation applied. Finally charge models are implemented in suitable drain current equation to study the electrical behavior of the device.

Charge density

10.1088/2053-1591/ab02c7

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Analytical model and simulation‐based analysis of a work function engineered triple metal tunnel field‐effect transistor device showing excellent device performance

IET Circuits Devices & Systems (2020)

Ria Bose J. N. Roy

In this study, the authors propose a work function engineered (WFE) triple metal (TM) tunnel field-effect transistor (TFET) device, which exhibits lower subthreshold slope (SS) and better on to off current ratio in comparison with conventional double gate TFET and dual metal TFET device. An analytical model is formulated to study the performance of the proposed device. A simulation-based study of these TFET devices has been carried out with the help of 2D TCAD (Technology Computer Aided Design) Sentaurus device simulator for different channel length values in order to validate our proposed mathematical model. The source side n + pocket in the proposed triple metal (TM) TFET device enhances tunnelling probability thus increasing on current and off current is controlled by another n-pocket near drain side. Significantly lower subthreshold slope (less than 10 mV/decade), high transconductance (in the order of 10−4 S/μm), low energy-delay product (24.601 fJ-ns/μm) obtained for TM WFE TFET makes this device more suitable for digital logic and RF (Radio Frequency) application.

Tunnel field-effect transistor

Subthreshold slope

Transconductance

Subthreshold conduction

10.1049/cds2.12009

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Semi-empirical modeling of rectangular triple gate FinFET incorporating the effect of 2D quantum confinement

Pratip Chakraborty Madhumita Das Sarkar Supratim Subhra Das Ria Bose Sabyasachi Sen

In this paper, the effect of configurational confinement of charge carriers in super thin body of undoped (or weakly doped) FinFET, is considered owing to development of a semi-empirical quantum model. Some significant short channel effects are also incorporated in our proposed model to characterize the device performance across specific range of operating voltages. Furthermore, the modeled curves are validated with respect to calibrated 3D simulation in ATLAS Silvaco.

Charge carrier

10.1109/devic57758.2023.10134990

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Evanescent mode based compact modelling of a dual‐metal double‐gate tunnel field‐effect transistor

IET Circuits Devices & Systems (2020)

Ria Bose J. N. Roy

In this study, channel potential for silicon-based doped dual-metal double-gate tunnel field-effect transistor structure is analytically solved using the evanescent-mode approach in the sub-threshold region. This method generally describes short channel effects in the entire channel region of the device structure and predicts different characteristic length which depends on tunnel current and does not depend along a transverse direction within the channel. The model is valid for the whole device structure rather than just semiconductor/insulator interfaces. The impact of variation of bias condition on channel potential is also investigated in the sub-threshold region. Finally, drain current is evaluated using Kane's and Kleysh's model and validated with a calibrated simulation, which has been carried out using 2D TCAD Sentaurus simulator.

Tunnel field-effect transistor

Double gate

10.1049/iet-cds.2019.0531

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2D Surface potential and mobility modelling of doped/undoped symmetric double gate MOSFET

IET Circuits Devices & Systems (2019)

Ria Bose Jitendra Nath Roy

The 2D surface potential and mobility models are proposed for symmetric doped/undoped channel double gate FET (DGFET) device. This is then used in drain current equation obtained by combining Pao-Sah's double integral formula with Pierret–Shields' type current model. The surface potential model and mobility model both are analytic and differently solved for both undoped and doped device. Being an explicit and continuous expression, the drain current model is used to describe the behaviour of the device at below and above threshold condition. Simulations are carried out using TCAD Sentaurus bundle of Synopsis tool. The accuracy of the proposed model is analysed and compared with the simulation result for different channel length and channel thickness value of the device.

Mobility model

Electron Mobility

Double gate

10.1049/iet-cds.2018.5100

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Citations (7)

Analytical 3D Surface Potential Model of a Junction-Based Triple-Gate MOSFET Device

IETE Technical Review (2021)

Ria Bose J. N. Roy

In this paper, a 3D potential model for a triple-gate Si MOSFET is derived in weak inversion using the variable separation technique based on a perimeter weighted approach. The channel potential is solved from Poisson’s equation along two different planes of the device separately and then using the same variable separation technique and proper boundary conditions 3D potential is addressed. Hence, the solution is not directly obtained from 3D Poisson's equation and does not involve any complex computation. The I-V model of the device is then predicted using the drift-diffusion technique. The accuracy of the model is checked with respect to commercial TCAD simulation results, and good agreement is observed. Our proposed model considers short-channel effects but does not find any quantum mechanical effects. The model result has also been compared with the industry-standard model to validate its performance. Due to its good accuracy, the model can be potentially invoked into a numerical simulator to predict the device's electrical behavior.

Poisson's equation

10.1080/02564602.2021.1927864

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Citations (1)

A 2D channel potential modelling of symmetric double-gate MOSFET at onset of threshold condition

International Journal of Electronics Letters (2019)

Ria Bose Jitendra Nath Roy

A two-dimensional (2D) channel potential distribution is analytically derived for lightly doped double-gate MOSFET at turn-on condition of the device by solving 2D Poisson’s equation with the application of suitable boundary condition. Threshold voltage roll-off is also modelled to predict the short channel behaviour of the device at sub-threshold condition. Our derived model closely follows the 2D numerical simulation without the inclusion of any fitting parameters. It also serves as a basic step towards computing the compact modelling of DG MOSFET at threshold condition.

Poisson's equation

Short-channel effect

Reverse short-channel effect

10.1080/21681724.2019.1661015

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