The successive approximation register (SAR) ADC is the most energy efficient architecture with moderate conversion rate and resolution. However, its comparator noise limits its resolution without sacrificing power efficiency. The delta-sigma modulator (DSM) is the most popular architecture for achieving high SNDR due to its oversampling, but the bulky operational amplifier (op-amp) makes it area inefficient. In LTE Advanced, the bandwidth (BW) of downlink ADCs needs to be configured according to the number of inter-band non-contiguous carrier aggregation (NCCA), which motivates us to combine the benefits of both architectures to reduce area and power consumption simultaneously with high SNDR. The noise-shaping SAR ADC [1] suppresses the comparison and quantization noise in signal BW using a simple cascaded FIR-IIR filter, which obviates the need for a power-hungry low-noise comparator or high-performance op-amp. To some extent, the noise-shaping SAR ADC is a hybrid of DSM and SAR ADCs. Hence, it has the potential to achieve the high resolution and good power efficiency of DSM and SAR ADCs, respectively. However, the passive sampling in an FIR filter introduces considerable thermal noise to the ADC, making it difficult to achieve a high SNR. This work presents an energy-efficient noise-shaping SAR ADC that uses a gain-enhanced dynamic amplifier and some capacitors to construct a low-noise dynamic FIR-IIR filter. The prototype achieves a peak SNDR of 79.74dB over a 5MHz BW with a power consumption of 0.46mW from a 1V supply.
Micro-milling, which is one of the mechanical micromachining methods, shows the potential to make very small parts with three dimensional microstructures. However, micro-milling is usually carried out on a traditional machine tool, which has a spindle with several kilowatts. For micro-milling on a traditional machine tool, most power is consumed by friction, not cutting, resulting in waste of energy. In this study, a miniature machine tool with a low-power spindle is used to improve the energy efficiency. The objective of this study is to investigate the feasibility of using current signal from a low-power spindle to estimate the tool life of a micro-milling tool. If signals regarding tool wear can be identified, product quality can be assured. Experimental results show that the current signal is effective to identify the tool wear in micro-milling with a low-power spindle.
This paper presents an energy-efficient successive approximation register (SAR)-assisted digital-slope analog-todigital converter (ADC) architecture for high-resolution applications. The proposed hybrid ADC combines a low-noise fine digital-slope ADC with a low-power coarse SAR ADC. The coarse SAR ADC rapidly approximates the input signal and produces a small residue signal for the succeeding fine ADC. The fine digital-slope ADC linearly approaches the small residue signal. A prototype was fabricated in 1P8M 28 nm CMOS technology. At 100 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio of 64.43 dB and a spurious free dynamic range of 75.42 dB at the Nyquist input frequency while consuming 0.35 mW from a 0.9 V supply. The resultant Walden and Schreier figures of merit are 2.6 fJ/conversion-step and 176.0 dB, respectively. The ADC occupies an active area of 66 μm × 71 μm.
A 10-MS/s-to-100-kS/s power-scalable fully differential comparator-based switched-capacitor (CBSC) 10-bit pipelined analog-to-digital converter (ADC) is presented. To operate over a wide range of sampling rates, an adaptive biasing technique is proposed to enhance both linearity and signal-to-noise-plus-distortion ratio (SNDR) at low sampling rates. This ADC has been fabricated in a 0.18-¿m standard CMOS process. It achieves 62.3-dB spurious-free-dynamic range (SFDR) and 53.3-dB SNDR while being sampled at 10 MS/s and consuming 1.95 mW from a 1.8-V power supply, which obtains a figure of merit of 510 fJ/step. With the utilization of adaptive biasing, the SNDR increases from 53.3 to 56.4 dB at most when decreasing the sampling rate. In addition, its power consumption continuously reduces from 1.95 mW (10 MS/s) to 158.4 ¿W (100 kS/s).
A 4th-order resistive feed-forward continuous time sigma-delta modulator (CTSDM) for a worldwide analog/digital TV-receiver is presented. The proposed hybrid integrator of the modulator is developed in order to save the summing amplifier and reduce total area. In addition, the modulator incorporates the proposed low power operational amplifiers (op-amp) with active feed-forward compensation to reduce power consumption in the loop filter. The prototype chip is implemented in a 55nm CMOS process which occupies 0.132 mm 2 . Measurements show that the proposed modulator achieves 80.2dB dynamic range, 75.1dB SNDR, and an effective number of bits (ENOB) of 12.2 bits over 5 MHz signal bandwidth. The figure of merit (FOM) is 0.28 pJ/conversion at 1.3 V supply.
In this brief, a fully differential comparator-based switched-capacitor (CBSC) second-order delta-sigma (DeltaSigma) modulator is presented. To ensure differential operation, the CBSC DeltaSigma modulator utilizes a common-mode feedback circuit to balance the pull-up current and the pull-down current in the ramp generator. This modulator has been fabricated in a standard 0.18-mum CMOS process. The active area is 0.21 mm 2 , and the power consumption, excluding output buffers, is 0.42 mW from a 1.8-V supply. This modulator achieves 65.3-dB signal-to-noise-plus-distortion ratio and an input dynamic range of 71 dB when sampled at 2.56 MS/s (OSR = 64).
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