Alex Pappachen James

University of Kerala

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Olga Krestinskaya

King Abdullah University of Science and Technology

Aidana Irmanova

Nazarbayev University

Kamilya Smagulova

King Abdullah University of Science and Technology

Irina Dolzhikova

Nazarbayev University

Akshay Kumar Maan

Nanyang Technological University

Mehdi Bagheri

Nazarbayev University

K. Saláma

King Abdullah University of Science and Technology

Kazybek Adam

Aalto University

Bhaskar Choubey

University of Siegen

Aswani Radhakrishnan

Digital Science (United States)

Cooperative Institutions

Weatherford College

161

Nazarbayev University

Institute of Electrical and Electronics Engineers

Canadian Standards Association

Michigan State University

Momoyama Gakuin University

Concordia University

University of Hawaiʻi at Mānoa

University of California, Los Angeles

Loyola University Maryland

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On-chip Face Recognition System Design with Memristive Hierarchical Temporal Memory

arXiv (Cornell University) (2017)

Timur Ibrayev Ulan Myrzakhan Olga Krestinskaya Aidana Irmanova Alex Pappachen James

Hierarchical Temporal Memory is a new machine learning algorithm intended to mimic the working principle of neocortex, part of the human brain, which is responsible for learning, classification, and making predictions. Although many works illustrate its effectiveness as a software algorithm, hardware design for HTM remains an open research problem. Hence, this work proposes an architecture for HTM Spatial Pooler and Temporal Memory with learning mechanism, which creates a single image for each class based on important and unimportant features of all images in the training set. In turn, the reduction in the number of templates within database reduces the memory requirements and increases the processing speed. Moreover, face recognition analysis indicates that for a large number of training images, the proposed design provides higher accuracy results (83.5\%) compared to only Spatial Pooler design presented in the previous works.

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Biologically inspired features used for robust phoneme recognition

International Journal of Machine Intelligence and Sensory Signal Processing (2013)

Mitar Milacic Alex Pappachen James Sima Dimitrijev

Formants are regarded as the basic building blocks of vowels; however, they are very rarely used as features for difficult automatic speech recognition tasks.Formant-based research is generally focused on formant extraction, because of the assumption that a better formant extraction method is the only manner to increase the effectiveness of formants.We challenge this assumption by investigating a different use of formants following their extraction.By using the same principles of combining formants as observed in speech perception studies, we create features that show good recognition performance under noisy testing conditions.Improved recognition performance with the proposed formant features is demonstrated by comparing to Mel-frequency cepstrum coefficients and perceptual linear predictive coding features on a hidden Markov model-based automatic speech recognition system.

10.1504/ijmissp.2013.052867

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Memristor-Based Synaptic Sampling Machines

Irina Dolzhikova K. Saláma Kizheppatt Vipin Alex Pappachen James

Synaptic Sampling Machine (SSM) is a type of neural network model that considers biological unreliability of the synapses. We propose the circuit design of the SSM neural network which is realized through the memristive-CMOS crossbar structure with the synaptic sampling cell (SSC) being used as a basic stochastic unit. The increase in the edge computing devices in the Internet of things era, drives the need for hardware acceleration for data processing and computing. The computational considerations of the processing speed and possibility for the real-time realization pushes the synaptic sampling algorithm that demonstrated promising results on software for hardware implementation.

Memristor

Realization (probability)

Hardware acceleration

10.1109/nano.2018.8626382

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ImageSplit: Modular Memristive Neural Network

2022 IEEE 22nd International Conference on Nanotechnology (NANO) (2022)

M Elamparithy R Chithra Alex Pappachen James

In this paper, we present an input regulated modular neural network architecture for realising large neural networks. The proposed network become scalable in design for hardware by splitting an input image into non-overlapping blocks to be processed individually by small sized neural network blocks. Classification is done by fusing the class decisions detected from each individual block. We test this approach on three different datasets using various deep neural network architectures. The analog computation of the proposed splitting technique were evaluated using memristive-crossbar neural network architectures in SPICE tool. The results obtained show that splitting and processing an image in multiple small sized network gives higher accuracy as compared to processing the image as a whole in a larger single network. The area and power requirements of the neural network hardware architecture with the proposed splitting technique was computed and compared with the non-splitting case.

Modular neural network

Memristor

10.1109/nano54668.2022.9928772

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Variability Analysis of Memristor-based Sigmoid Function

International Conference on Computing and Network Communications (2018)

Nursultan Kaiyrbekov Olga Krestinskaya Alex Pappachen James

Activation functions are widely used in neural networks to decide the activation value of the neural unit based on linear combinations of the weighted inputs. The effective implementation of activation function is highly important to enhance he performance of a neural network. One of the most widely used activation functions is sigmoid. Therefore, there is a growing interest to enhance the performance of sigmoid circuits. In this paper, the main objective is to modify existing current mirror based sigmoid model by replacing CMOS transistors with memristive devices. We present the performance, variation of transistor sizes and temperature. The area, power and noise in the modified CMOS-memristive sigmoid circuit are shown. The application of memristors in the sigmoid circuit ensures the reduction of on-chip area, and power dissipation by 7%. The proposed sigmoid circuit was simulated in SPICE using TSMC 180nm CMOS design process.

Sigmoid function

Memristor

Activation function

Spice

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IEEE Transactions on Circuits and Systems—I:Regular Papers publication information

IEEE Transactions on Circuits and Systems I Regular Papers (2019)

Reza Azarderakhsh Alessandro Cilardo Danilo Comminiello Luis Hernández Jovanovic Gordana

10.1109/tcsi.2019.2925747

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Analog Spike-Based Multi-Head Attention with Memristor Crossbar Arrays for Text Classification

IEEE transactions on circuits and systems for artificial intelligence. (2024)

Veena Dinesh Aswani Radhakrishnan Alex Pappachen James

Memristor

10.1109/tcasai.2024.3520011

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Speech Signal Analysis for the Estimation of Heart Rates Under Different Emotional States

arXiv (Cornell University) (2016)

Aibek Ryskaliyev Sanzhar Askaruly Alex Pappachen James

A non-invasive method for the monitoring of heart activity can help to reduce the deaths caused by heart disorders such as stroke, arrhythmia and heart attack. The human voice can be considered as a biometric data that can be used for estimation of heart rate. In this paper, we propose a method for estimating the heart rate from human speech dynamically using voice signal analysis and by the development of an empirical linear predictor model. The correlation between the voice signal and heart rate are established by classifiers and prediction of the heart rates with or without emotions are done using linear models. The prediction accuracy was tested using the data collected from 15 subjects, it is about 4050 samples of speech signals and corresponding electrocardiogram samples. The proposed approach can use for early non-invasive detection of heart rate changes that can be correlated to an emotional state of the individual and also can be used as a tool for diagnosis of heart conditions in real-time situations.

SIGNAL (programming language)

Human heart

10.48550/arxiv.1608.03720

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Binary Weighted Memristive Analog Deep Neural Network for Near-Sensor Edge Processing

arXiv (Cornell University) (2018)

Olga Krestinskaya Alex Pappachen James

The memristive crossbar aims to implement analog weighted neural network, however, the realistic implementation of such crossbar arrays is not possible due to limited switching states of memristive devices. In this work, we propose the design of an analog deep neural network with binary weight update through backpropagation algorithm using binary state memristive devices. We show that such networks can be successfully used for image processing task and has the advantage of lower power consumption and small on-chip area in comparison with digital counterparts. The proposed network was benchmarked for MNIST handwritten digits recognition achieving an accuracy of approximately 90%.

MNIST database

Memristor

Backpropagation

Neuromorphic engineering

10.48550/arxiv.1808.00737

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An overview of memristive cryptography

arXiv (Cornell University) (2019)

Alex Pappachen James

Smaller, smarter and faster edge devices in the Internet of things era demands secure data analysis and transmission under resource constraints of hardware architecture. Lightweight cryptography on edge hardware is an emerging topic that is essential to ensure data security in near-sensor computing systems such as mobiles, drones, smart cameras, and wearables. In this article, the current state of memristive cryptography is placed in the context of lightweight hardware cryptography. The paper provides a brief overview of the traditional hardware lightweight cryptography and cryptanalysis approaches. The contrast for memristive cryptography with respect to traditional approaches is evident through this article, and need to develop a more concrete approach to developing memristive cryptanalysis to test memristive cryptographic approaches is highlighted.

Financial cryptography

Strong cryptography

10.48550/arxiv.1906.00574

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