F. Muller

Technical University of Munich

Author Statistics

Papers

Citation

H-Index

i-10 index

Research Trends

Author Order

Document Type

Co-Authors

Walter Stechele

Technical University of Munich

Christopher Claus

California State University, Stanislaus

Tapan Kumar Saha

University of Queensland

Johannes Zeppenfeld

Technical University of Munich

P. Purkait

Jadavpur University

T. Fowler

European Organization for Nuclear Research

Olivier Muller

Techniques of Informatics and Microelectronics for Integrated Systems Architecture

Christoph Baumhof

Hyperstone (Germany)

Tobias Stadlbauer

European Organization for Nuclear Research

Markus Lienkamp

Technical University of Munich

Cooperative Institutions

Technical University of Munich

European Organization for Nuclear Research

Centre National de la Recherche Scientifique

Hyperstone (Germany)

Karlsruhe Institute of Technology

University of Queensland

Queensland University of Technology

Ludwig-Maximilians-Universität München

Fraunhofer Institute for Integrated Circuits

Bayer (Germany)

Author Statistics

Papers

Citation

H-Index

i-10 index

Research Field

Off-line placement/scheduling of hardware tasks on reconfigurable devices

HAL (Le Centre pour la Communication Scientifique Directe) (2010)

Ikbel Belaid Mondher Benjemaa F. Muller

Processor scheduling

Reconfigurable Computing

Source

Cite

Citations (0)

Techno-economic design of battery thermal management systems in different climates

Journal of Energy Storage (2022)

Olaf Teichert F. Muller Markus Lienkamp

Installation

Warranty

10.1016/j.est.2021.103832

Cite

Citations (10)

A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration

Christopher Claus F. Muller Johannes Zeppenfeld Walter Stechele

The Xilinx Virtex family of FPGAs provides the ability to perform partial run-time reconfiguration, also known as dynamic partial reconfiguration (DPR). Taking this concept one step further, partial dynamic self-reconfiguration becomes possible through the internal configuration access port (ICAP). In this paper a framework for lowering reconfiguration times using the combitgen tool to reduce the overhead found within bitstreams, along with a completely new, very simple and area efficient ICAP controller that is connected directly to the processor local bus (PLB) and is equipped with direct memory access (DMA) capabilities is presented. Using this PLB Master ICAP controller, it is possible to reach the maximum practical throughput that can be achieved with the ICAP interface of Virtex-II Pro devices. Compared to an alternative realization using the OPBHWICAP provided by Xilinx (a slave attachment on the on-chip peripheral bus), it is possible to achieve improvements concerning reconfiguration times by a factor of 20.

Control reconfiguration

Virtex

10.1109/ipdps.2007.370362

Cite

Citations (77)

Combitgen: A new approach for creating partial bitstreams in Virtex-II Pro.

ARCS Workshops (2006)

Christopher Claus F. Muller Walter Stechele

Virtex

Source

Cite

Citations (15)

A novel 32 bit RISC architecture unifying RISC and DSP

IEEE International Conference on Acoustics Speech and Signal Processing (2002)

Christoph Baumhof F. Muller Olivier Muller M. Shlett

A novel 32 bit RISC architecture is presented which is the basis of a powerful general purpose microprocessor and in parallel a 16/32 bit fixed point DSP processor. This unifying of RISC and DSP was not achieved by simply using a microprocessor and DSP core, but a new concept for the implementation of DSP processors has been developed. With the architecture presented, it is proven that a DSP processor can be implemented by strictly using the RISC design philosophy. Besides providing basic 16 bit fixed point functionality, the architecture implements a set of DSP instructions that support an efficient mapping of common DSP algorithms to the processor.

Microprocessor

Texas Instruments DaVinci

32-bit

16-bit

Addressing mode

Microarchitecture

10.1109/icassp.1997.599836

Cite

Citations (1)

An attempt to correlate time & frequency domain polarisation measurements for the insulation diagnosis of power transformer

IEEE Power Engineering Society General Meeting, 2004. (2005)

Tapan Kumar Saha P. Purkait F. Muller

The insulation system of power transformers (oil and paper/pressboard) generally change their dielectric properties during the life of the transformer and dielectric measurements have therefore been applied to assess the quality or state of ageing of the system. Both time domain and frequency domain dielectric diagnosis techniques have recently gained popularity in providing information on the condition of transformer oil-paper insulation. The present paper aims at deriving a correlation between these two methods of diagnosis. Simulation results along with actual field test results have demonstrated a direct correlation between the time and frequency domain tools for insulation diagnosis.

Pressboard

Insulation system

Dissolved Gas Analysis

10.1109/pes.2004.1373188

Cite

Citations (12)

Using partial-run-time reconfigurable hardware to accelerate video processing in driver assistance system

Christopher Claus Johannes Zeppenfeld F. Muller Walter Stechele

In this paper we show a reconfigurable hardware architecture for the acceleration of video-based driver assistance applications in future automotive systems. The concept is based on a separation of pixel-level operations and high level application code. Pixel-level operations are accelerated by coprocessors, whereas high level application code is implemented fully programmable on standard PowerPC CPU cores to allow flexibility for new algorithms. In addition, the application code is able to dynamically reconfigure the coprocessors available on the system, allowing for a much larger set of hardware accelerated functionality than would normally fit onto a device. This process makes use of the partial dynamic reconfiguration capabilities of Xilinx Virtex FPGAs.

Coprocessor

Control reconfiguration

Hardware acceleration

PowerPC

Reconfigurable Computing

Virtex

ARM architecture

Code (set theory)

10.5555/1266366.1266473

Cite

Citations (56)

Deriving an Equivalent Circuit of Transformers Insulation for Understanding the Dielectric Response Measurements

IEEE Transactions on Power Delivery (2005)

Tapan Kumar Saha P. Purkait F. Muller

Preventive diagnosis and maintenance of transformers have become more and more popular in recent times in order to improve the reliability of electric power systems. Dielectric testing techniques such as return voltage measurement (RVM) and polarization-depolarization current (PDC) measurement are being investigated as potential tools for condition assessment of transformer insulation. A better understanding and analysis of the dielectric test results are only possible with a clear understanding of the physical behavior of the insulation system in response to moisture and aging. A circuit model, which describes the dielectric behavior of the transformer's main insulation system, has been parameterized in this paper. The values of the parameters of the model have been identified from the dielectric tests. A correlation has been developed between the physical condition of the insulation and the equivalent model parameters that enable a clear and transparent interpretation of the dielectric test results.

Dielectric withstand test

Insulation system

Dielectric response

10.1109/tpwrd.2004.835436

Cite

Citations (241)

Optimization potential of CMOS power by wire spacing

GI Jahrestagung (1) (2005)

Paul Zuber F. Muller Walter Stechele

In this work, we identify the power-optimal wire spacing as a geometric program. Its solution is a vector of individual distances between the wires. To quantify the optimization potential by this method we model the output of a grid based router with a set of parallel wires. A comparison of the power values before and after geometric optimization shows that the optimization potential lies well in the two digit percent zone for a representative circuit model in a 130nm process.

Power grid

Source

Cite

Citations (2)

DESIGN AND MEASUREMENTS OF A FAST HIGH VOLTAGE PULSE GENERATOR FOR THE MEDAUSTRON LOW ENERGY TRANSFER LINE FAST DEFLECTOR

T. Fowler Michael Barnes Thomas Krämer F. Muller Tobias Stadlbauer

MedAustron, a centre for ion-therapy and research, will comprise an accelerator facility based on a synchrotron for the delivery of protons and light ions for cancer treatment. The Low Energy Beam Transfer line (LEBT) to the synchrotron contains an electrostatic fast deflector (EFE) which, when energized, deviates the continuous beam arriving from the ion source onto a Faraday Cup: the specified voltage is ±3.5 kV. De-energizing the EFE for variable pulse durations from 500 ns up to d.c. allows beam passage for multi-turn injection into the synchrotron. To maintain beam quality in the synchrotron, the EFE pulse generator requires rise and fall times of less than 300 ns between 90 % of peak voltage and a ±1 V level. To achieve this, a pulsed power supply (PKF), with high voltage MOSFET switches connected in a push-pull configuration, will be mounted in close proximity to the deflector itself. A fast, large dynamic range monitoring circuit will verify switching to the ±1 V level and subsequent flat bottom pulse quality. A prototype will be installed in the injector test stand in 2012; this paper presents the design and first measurements of the PKF and its monitoring circuit.

Faraday cup

Transfer line

Source

Cite

Citations (1)