Andreas Genser

Graz University of Technology

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Christian Steger

Graz University of Technology

Josef Haid

Infineon Technologies (Austria)

Christian Bachmann

Imec the Netherlands

Reinhold Weiß

Federal Institute for Vocational Education and Training

Norbert Druml

Infineon Technologies (Austria)

Holger Bock

Infineon Technologies (Austria)

Armin Krieg

Infineon Technologies (Germany)

Manuel Menghin

Graz University of Technology

R. Weiß

Leipzig University

Johannes Grinschgl

Graz University of Technology

Cooperative Institutions

Graz University of Technology

Infineon Technologies (Austria)

Institute of Informatics of the Slovak Academy of Sciences

University of Graz

Institut für Technische und Angewandte Physik (Germany)

Infineon Technologies (Germany)

Imec the Netherlands

Holst Centre (Netherlands)

Delft University of Technology

Saarland University

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Emulation-Based Test and Verification of a Design's Functional, Performance, Power, and Supply Voltage Behavior

Norbert Druml Manuel Menghin Christian Steger R. Weiß Andreas Genser

Test and verification are essential parts during a product's development cycle. Simulation and emulation are well known techniques to test and verify the functionality of a design-under-test (DUT) before its tape-out. However, there are additional issues like peak power consumption and supply voltage drops, which can compromise a hardware's functionality. These issues are only partly covered by nowadays functional hardware emulation test and verification approaches. This paper presents a comprehensive emulation methodology. It combines functional hardware emulation with model-based performance, power, and supply voltage analysis techniques. The DUT, which has to be available in a hardware description language, is integrated into a FPGA along with designated analysis units. These analysis units implement models of the DUT's performance, power consumption, and supply voltage behavior. The presented emulation methodology allows a designer to test designs in such a way that the cycle accurate results are taken online, in real-time, and verify both functional and performance behavior, as well as power consumption and supply voltage levels. The proposed comprehensive emulation methodology is used, as an example of application, to verify the design of a LEON3 multi-core processor system as well as a RF-powered contacatless smart card. The depicted results demonstrate that this emulation approach is suitable to detect functional misbehavior caused by power and supply voltage hazards and how they influence the performance of the system.

Hardware emulation

Device under test

Automatic test equipment

10.1109/pdp.2013.54

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Citations (5)

Solutions for Cyber-Physical Systems Ubiquity

Norbert Druml Andreas Genser Armin Krieg Manuel Menghin Andrea Hoeller

Cyber-physical system

Source

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Citations (1)

An Automated Framework for Power-Critical Code Region Detection and Power Peak Optimization of Embedded Software

Lecture notes in computer science (2011)

Christian Bachmann Andreas Genser Christian Steger Reinhold Weiß Josef Haid

Code (set theory)

10.1007/978-3-642-17752-1_2

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Citations (3)

Rapid System-Level Power Estimation for Power-Aware Embedded Software Design

Christian Bachmann Andreas Genser Christian Steger Josef Haid Reinhold Weiß

Source

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Citations (1)

Power-Aware Software Development Based on Power Emulation

Christian Bachmann Andreas Genser Christian Steger Reinhold Weiß Josef Haid

Source

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Citations (0)

Supply voltage emulation platform for DVFS voltage drop compensation explorations

Andreas Genser Christian Bachmann Christian Steger Reinhold Weiß Josef Haid

The supply voltage level has emerged as an important metric alongside power consumption information to investigate system stability and reliability issues. In this paper, we propose a supply voltage emulation platform based on a power emulation approach to derive real-time power and supply voltage information from a system. Moreover, we present a dynamic voltage and frequency scaling (DVFS) based voltage drop compensation scheme to maintain stable system operation. The early design phase applicability of our emulation-based approach enables the investigation of the effectiveness of voltage drop compensation schemes before the final chip is available.

Voltage drop

CPU core voltage

Voltage reduction

10.1109/ispass.2011.5762727

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Citations (5)

Characterization and handling of low-cost micro-architectural signatures in MPSoCs

Armin Krieg Johannes Grinschgl Christian Steger Reinhold Weiß Andreas Genser

In recent years the wide spread introduction of small embedded systems into every corner of everyday life lead to the strong need for highly reliable and secure computing machines. These machines now affect the safety of humans as well as the security of personal data and consequently money transactions. To ensure the integrity of these systems' operating state, several fault detection mechanisms have been developed to safely correct or stop unforeseen execution behavior. Because of the rise of battery or even field-supplied systems these mechanisms often heavily decrease available power budgets or lead to significantly increased production costs. Therefore, this paper introduces novel micro-architectural execution signature characterization and handling techniques for system-on-chip designs providing power estimation hardware. Existing power sensor infrastructure is reused to enable efficient system-state monitoring using micro-architectural hashes to cover a wide range of implemented system functionality. Reduced hashing implementations are characterized for their fault detection efficiency. This hardware-based approach provides a completely transparent solution to counteract faults resulting from emerging wearout defects or intentional attacks on the execution integrity.

Implementation

10.1109/ets.2012.6233011

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Citations (4)

A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing

Christian Bachmann Andreas Genser Jos Hulzink Mladen Bereković Christian Steger

The IEEE 802.15.4a amendment has introduced ultra-wideband impulse radio (UWB IR) as a promising physical layer for energy-efficient, low data rate communications. A critical part of the UWB IR receiver design is the low-power implementation of the digital baseband processing required for synchronization and data decoding. In this paper we present the development of an application-specific instruction-set processor (ASIP) that is tailored to the requirements defined by the baseband algorithms. We report a number of optimizations applied to the algorithms as well as to the hardware architecture. This enables performance increases up to a factor of 122x and energy consumption decreases up to 90x as compared to a 16-bit baseline architecture. Furthermore, this ASIP offers greater flexibility due to programmability as compared to an ASIC implementation.

Application-specific integrated circuit

Wideband

10.1109/date.2009.5090922

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Citations (3)

A Hardware-Accelerated Estimation-Based Power Profiling Unit - Enabling Early Power-Aware Embedded Software Design and On-Chip Power Management

Lecture notes in computer science (2019)

Andreas Genser Christian Bachmann Christian Steger Reinhold Weiß Josef Haid

Profiling (computer programming)

Embedded software

Power budget

10.1007/978-3-662-58834-5_4