B. Prathiba

Raisoni Group of Institutions

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V. Sumalatha

Vels University

K. Jaya Sankar

Methodist University

Nagnath B. Hulle

Raisoni Group of Institutions

Sarika R. Khope

Vellore Institute of Technology University

K. Anuradha

Dr. M.G.R. Educational and Research Institute

E. Lakshmi Prasad

Jawaharlal Nehru Technological University Anantapur

Yogini Borole

Research & Development Establishment (Engrs.)

D. Kotambkar

Cooperative Institutions

Institute of Engineering

Raisoni Group of Institutions

Osmania University

Jawaharlal Nehru Technological University Anantapur

Arunai Engineering College

Dr. M.G.R. Educational and Research Institute

SASTRA University

Jawaharlal Nehru Technological University, Hyderabad

Karpagam Academy of Higher Education

Vels University

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SDQE: Sensor Data Quality Enhancement in Reconfigurable Network for Optimal Reliability

Advances in intelligent systems and computing (2018)

B. Prathiba K. Jaya Sankar V. Sumalatha

Synchronizing

10.1007/978-3-319-91192-2_35

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Citations (1)

Optimized architecture for SNOW 3G

International Journal of Power Electronics and Drive Systems/International Journal of Electrical and Computer Engineering (2020)

Nagnath B. Hulle B. Prathiba Sarika R. Khope K. Anuradha Yogini Borole

SNOW 3G is a synchronous, word-oriented stream cipher used by the 3GPP standards as a confidentiality and integrity algorithms. It is used as first set in long term evolution (LTE) and as a second set in universal mobile telecommunications system (UMTS) networks. The cipher uses 128-bit key and 128 bit IV to produce 32-bit ciphertext. The paper presents two techniques for performance enhancement. The first technique uses novel CLA architecture to minimize the propagation delay of the 2<sup>32</sup> modulo adders. The second technique uses novel architecture for S-box to minimize the chip area. The presented work uses VHDL language for coding. The same is implemented on the FPGA device Virtex xc5vfx100e manufactured by Xilinx. The presented architecture achieved a maximum frequency of 254.9 MHz and throughput of 7.2235 Gbps.

Virtex

UMTS frequency bands

10.11591/ijece.v11i1.pp545-557

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A Novel Clustering Algorithm for Leveraging Data Quality in Wireless Sensor Network

Communications in computer and information science (2018)

B. Prathiba K. Jaya Sankar V. Sumalatha

10.1007/978-981-10-8657-1_53

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Novel framework of retaining maximum data quality and energy efficiency in reconfigurable wireless sensor network

Zenodo (CERN European Organization for Nuclear Research) (2019)

B. Prathiba K. Jaya Sankar V. Sumalatha

10.11591/ijece.v9i4.pp2983-2901

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Novel framework of retaining maximum data quality and energy efficiency in reconfigurable wireless sensor network

International Journal of Electrical and Computer Engineering (IJECE) (2019)

B. Prathiba K. Jaya Sankar V. Sumalatha

There are various unseen and unpredictable networking states in Wireless Sensor Network (WSN) that adversely affect the aggregated data quality. After reviewing the existing approaches of data quality in WSN, it was found that the solutions are quite symptomatic and they are applicable only in a static environment; however their successful applicability on dynamic and upcoming reconfigurable network is still a big question. Moreover, data quality directly affects energy conservation among the nodes. Therefore, the proposed system introduces a simple and novel framework that jointly addresses the data quality and energy efficiency using probability-based design approach. Using a simplified analytical methodology, the proposed system offers solution in the form of selection transmission of an aggergated data on the basis of message priority in order to offer higher data utilization factor. The study outcome shows proposed system offers a good balance between data quality and energy efficiency in contrast to existing system.

10.11591/ijece.v9i4.pp2893-2901

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FPGA Implementation of Smart Cryptography Algorithm

International Journal of Recent Technology and Engineering (IJRTE) (2020)

B. Prathiba E. Lakshmi Prasad Nagnath B. Hulle Sarika R. Khope

Mceliece algorithm is one of the simplest algorithm which is widely used in cryptography application for encrypting and decrypting the data. In the proposed work, mceliece algorithm able to allow an infinite number of characters, but for every nine characters, it considered as one iteration due to the fixed length of matrix size (3*3). Findings: This mceliece application running over micro blaze processor, and this processor implemented on Spartan-3E FPGA. The entire experimental setup is implemented using Xilinx platform studio 14.3 and targeted on Spartan 3E-1600E FPGA.

Spartan

McEliece Cryptosystem

10.35940/ijrte.e6126.018520

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Hardware Optimization and FPGA Implementation of Pipelined ZUC Architecture

2021 IEEE 6th International Conference on Computing, Communication and Automation (ICCCA) (2021)

Nagnath B. Hulle B. Prathiba Sarika R. Khope

The ZUC stream cipher belongs to synchronous stream cipher category. The cipher is word oriented and produces two words (32-bits) cipher text per cycle. The ZUC uses 128 bits key and 128-bits Initialization Vector (IV) for its operation. The research work considers FPGA implementation of pipelined ZUC architecture. The presented work uses compact architecture for modulo adders (over 2 ³¹ -1) used in feedback path and modulo adders (Over 2 ³² ) used in Finite State Machine (FSM). It also uses novel S-box architectures to minimize hardware resources. The presented architecture coded using VHDL language using Xilinx ISE 14.2 software for synthesis and simulation. The hardware implementation of the design uses Xilinx FPGA Virtex-5 XC5VFX130T having package FF1738. The presented hardware attained throughput of 5411.8 Mbps at clock frequency of 169.119MHz. The result shows the considerable hardware optimization.

Virtex

10.1109/iccca52192.2021.9666269

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Enhancing the data quality in wireless sensor networks — A review

B. Prathiba K. Jaya Sankar V. Sumalatha

The area of wireless sensor network (WSN) has always been the pivotal point of attention for various researchers for more than a decade. Although WSN is featured with various advantageous characteristics, still it is shrouded with various issues that dampen the spirit of researchers. Various significant problems that are being addressed in the literature are energy issues, security issues, bandwidth issues, routing issues, etc. This paper emphasizes the issues of data quality from the data aggregation or fusion process in wireless sensor network. The paper has presented a simple description of data, its essential characteristics, and has discussed some of the significant literature that discusses about enhancing the data quality as well as fault tolerant system in wireless sensor network. Finally, the paper briefs about the research gap that has been identified from the literature review.

Sensor Fusion

10.1109/icacdot.2016.7877626

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Citations (13)

Compact Reconfigurable Architecture for Sosemanuk Stream Cipher

International Journal of Engineering and Advanced Technology (2020)

Nagnath B. Hulle B. Prathiba Sarika R. Khope

Sosemanuk is word oriented synchronous stream cipher capable to produce 32 bit ciphertext. It uses variable key from 128 bit to 256 bit and publically known Initialization Vector (IV) of 128 bit. Sosemanuk is one of the finalists in Profile 1 of the eSTREAM Portfolio. This cipher targets to avoid structural properties of SNOW2.0 to improve its efficiency by reducing the internal state size. It also uses reduced round Serpent24 block cipher to provide secure and efficient key loading process. This paper presents compact architecture for Sosemanuk stream cipher. The proposed architecture uses compact S-box architecture and compact modulo adders designed using CLA. The proposed compact S-box minimizes resources utilized without affecting performance. Proposed modulo adder architecture minimizes resources used as compared to conventional CLA implementation. The algorithm was designed by using VHDL language with CAD tool Xilinx ISE design suite 13.2 and implemented on Xilinx Virtex XC5VFX100E FPGA device. The proposed architecture achieved throughput of 4.281 Gbps at clock frequency of 133.788 MHz

10.35940/ijeat.c5252.029320

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Citations (3)