Alex Wynn

MIT Lincoln Laboratory

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L. M. Johnson

MIT Lincoln Laboratory

Vladimir Bolkhovsky

MIT Lincoln Laboratory

Sergey K. Tolpygo

Massachusetts Institute of Technology

Evan Golden

Massachusetts Institute of Technology

Scott Zarr

MIT Lincoln Laboratory

M.A. Gouker

Massachusetts Institute of Technology

Ravi Rastogi

MIT Lincoln Laboratory

Alexandra Day

Northwestern University

Timothy Sherwood

University of California, Santa Barbara

Terence J. Weir

MIT Lincoln Laboratory

Cooperative Institutions

Massachusetts Institute of Technology

MIT Lincoln Laboratory

National Institute of Standards and Technology

Quantum Devices (United States)

Karlsruhe Institute of Technology

Vanderbilt University

Sandia National Laboratories

Hypres (United States)

Cornell University

Sandia National Laboratories California

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Wafer-Scale Characterization of a Superconductor Integrated Circuit Fabrication Process, Using a Cryogenic Wafer Prober

IEEE Transactions on Applied Superconductivity (2022)

Joshua T. West A. Kurlej Alex Wynn Chad S. Rogers M.A. Gouker

Using a fully automated cryogenic wafer prober, we measured superconductor fabrication process control monitors and simple integrated circuits on 200-mm wafers at 4.4 K, including SQIF-based magnetic field sensors, SQUID-based circuits for measuring inductors, Nb/Al-AlO _x /Nb Josephson junctions, test structures for measuring critical current of superconducting wires and vias, resistors, etc., to demonstrate the feasibility of using the system for characterizing niobium superconducting devices and integrated circuits on a wafer scale. Data on the wafer-scale distributions of the residual magnetic field, junction tunnel resistance, energy gap, inductance of multiple Nb layers, and critical currents of interlayer vias are presented. A comparison with existing models is made. The wafers were fabricated in the SFQ5ee process, the fully planarized process with eight niobium layers and a layer of kinetic inductors, developed for superconductor electronics at MIT Lincoln Laboratory, Lexington, MA, USA. The cryogenic wafer prober was developed at HPD/FormFactor, Inc., Boulder, CO, USA.

Kinetic inductance

10.1109/tasc.2022.3172660

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Citations (8)

Automatic 4 K Cryogenic Probe Station for DC and Microwave Measurements on 150-mm and 200-mm Wafers

2022 IEEE/MTT-S International Microwave Symposium - IMS 2022 (2022)

Joshua T. West A. Kurlej Alex Wynn Chad Rogers M.A. Gouker

Robust maturation of cryogenic electronics has been limited by the lack of high-throughput measurement capabilities, especially for electronics that operate at 4 K. Automated on-wafer probing to characterize the dc and RF performance of components and complete circuits has been a critical element in the development of room temperature electronics. We report here the development of a fully automated wafer prober that operates with the wafer cooled to a temperature of 4 K and has the ability to null the ambient magnetic field to below 100 nT, which is important for measuring superconducting circuits with the wafer prober.

Cryogenics

10.1109/ims37962.2022.9865525

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Citations (1)

Synaptic weighting in single flux quantum neuromorphic computing

Scientific Reports (2020)

Michael L. Schneider Christine A. Donnelly Ian W. Haygood Alex Wynn Stephen E. Russek

Abstract Josephson junctions act as a natural spiking neuron-like device for neuromorphic computing. By leveraging the advances recently demonstrated in digital single flux quantum (SFQ) circuits and using recently demonstrated magnetic Josephson junction (MJJ) synaptic circuits, there is potential to make rapid progress in SFQ-based neuromorphic computing. Here we demonstrate the basic functionality of a synaptic circuit design that takes advantage of the adjustable critical current demonstrated in MJJs and implement a synaptic weighting element. The devices were fabricated with a restively shunted Nb/AlO x -Al/Nb process that did not include MJJs. Instead, the MJJ functionality was tested by making multiple circuits and varying the critical current, but not the external shunt resistance, of the oxide Josephson junction that represents the MJJ. Experimental measurements and simulations of the fabricated circuits are in good agreement.

Neuromorphic engineering

Magnetic flux quantum

10.1038/s41598-020-57892-0

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Citations (28)

Addressable superconductor integrated circuit memory from delay lines

Scientific Reports (2023)

Jennifer Volk Alex Wynn Evan Golden Timothy Sherwood Georgios Tzimpragos

Abstract Recent advances in logic schemes and fabrication processes have renewed interest in using superconductor electronics for energy-efficient computing and quantum control processors. However, scalable superconducting memory still poses a challenge. To address this issue, we present an alternative to approaches that solely emphasize storage cell miniaturization by exploiting the minimal attenuation and dispersion properties of superconducting passive transmission lines to develop a delay-line memory system. This fully superconducting design operates at speeds between 20 and 100 GHz, with ± 24% and ± 13% bias margins, respectively, and demonstrates data densities in the 10s of Mbit/cm 2 with the MIT Lincoln Laboratory SC2 fabrication process. Additionally, the circulating nature of this design allows for minimal control circuitry, eliminates the need for data splitting and merging, and enables inexpensive implementations of sequential access and content-addressable memories. Further advances in fabrication processes suggest data densities of 100s of Mbit/cm 2 and beyond.

Megabit

10.1038/s41598-023-43205-8

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Citations (2)

Integrated Superconducting Transition-Edge-Sensor Energy Readout (ISTER)

IEEE Transactions on Applied Superconductivity (2023)

S. W. Leman Evan Golden Matthew C. Guyton Kevin Ryu Alex Wynn

We describe a million-pixel-scale multiplexed readout for superconducting Transition Edge Sensor (TES) microcalorimeters, using Rapid Single Flux Quantum (RSFQ) digital circuits. Depending on the application and the power dissipation requirements, the readout circuits may be either fabricated on the same wafer as the TES or integrated with the TES wafer using a multichip module, thereby integrating the TES and readout circuits. A data reduction scheme in the RSFQ circuits is described, using integrating counters to measure the TES pulse area. Power and clock requirements for measuring a large number of TES channels per readout line are discussed. Basic components of the ISTER readout circuit have been fabricated in the SFQ5ee process at MIT Lincoln Laboratory and operated at 4 K. The fabrication process has eight fully planarized Nb layers and one layer of Nb/Al-AlOx/Nb Josephson junctions with 100

$\mu$

$^{2}$

critical current density. Simulations of a TES read out are performed to investigate possible limits on energy resolution using ISTER.

10.1109/tasc.2023.3271276

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Citations (2)

Advanced Fabrication Processes for Superconducting Very Large Scale Integrated Circuits

IEEE Transactions on Applied Superconductivity (2016)

Sergey K. Tolpygo Vladimir Bolkhovsky Terence J. Weir Alex Wynn D.E. Oates

We review the salient features of two advanced nodes of an 8-Nb-layer fully planarized process developed recently at MIT Lincoln Laboratory for fabricating Single Flux Quantum(SFQ) digital circuits with very large scale integration on 200-mm wafers: the SFQ4ee and SFQ5ee nodes, where 'ee' denotes the process is tuned for energy efficient SFQ circuits. The former has eight superconducting layers with 0.5 {\mu}m minimum feature size and a 2 {\Omega}/sq Mo layer for circuit resistors. The latter has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm and a thin superconducting MoNx layer (Tc ~ 7.5 K) with high kinetic inductance (about 8 pH/sq) for forming compact inductors. A nonsuperconducting (Tc < 2 K) MoNx layer with lower nitrogen content is used for 6 {\Omega}/sq planar resistors for shunting and biasing of Josephson junctions. Another resistive layer is added to form interlayer, sandwich-type resistors of m{\Omega} range for releasing unwanted flux quanta from superconducting loops of logic cells. Both process nodes use Au/Pt/Ti contact metallization for chip packaging. The technology utilizes one layer of Nb/AlOx-Al/Nb JJs with critical current density, Jc of 100 {\mu}A/{\mu}m^2 and minimum diameter of 700 nm. Circuit patterns are defined by 248-nm photolithography and high density plasma etching. All circuit layers are fully planarized using chemical mechanical planarization (CMP) of SiO2 interlayer dielectric. The following results and topics are presented and discussed: the effect of surface topography under the JJs on the their properties and repeatability, critical current and Jc targeting, effect of hydrogen dissolved in Nb, MoNx properties for the resistor layer and for high kinetic inductance layer, technology of m{\Omega}-range resistors.

Resistive touchscreen

Kinetic inductance

10.1109/tasc.2016.2519388

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Citations (106)

Waferscale S-MCM for High Performance Computing

Rabindra Nath Das Vladimir Bolkhovsky Alex Wynn Ravi Rastogi Scott Zarr

This paper describes a novel strategy to combine laser direct write (LDW) and optical lithography (I-line) to fabricate 200 mm waferscale superconducting multi-chip modules (S-MCM) for interconnecting multiple active superconducting electronics chips based on single flux quantum (SFQ) logic for next generation cryogenic processing systems. The packaging roadmap includes the development of S-MCM (48 mm x 48 mm) using a nearly full I-line reticles, followed by reticle stitching to fabricate the largest possible stitched S-MCM (96 mm x 96 mm) using a four mask/layer process. The stitching process starts with sequential exposure of multiple I-line photomasks, with small overlap (stitched area), to realize larger combined circuit areas for design- critical S-MCM layers with minimum linewidths of 0.8-1 gm. The packaging roadmap further extends the S-MCM size utilizing laser direct write (LDW) lithography to make wider (> 1 gm) features such as fan-out circuits, extending the stitched circuit area to include the entire 200 mm wafer as a single S-MCM. Process control monitors (PCM) include snake/comb test structures, critical dimension (CD) cells, transmission lines, daisy chains etc. Niobium-indium-based microbump technology was developed to demonstrate full-size (20 x 20 mm ² ) SFQ flip-chips on an S-MCM with low 4 K interconnect resistance (50-100 μΩ) at the SFQ chip to S-MCM interface. Confocal micrographs show a uniform niobium-indium microbump-based interconnect network and X-ray images show the desired deformation of niobiumindium microbumps after flip-chip bonding. Full-size (20x20mm ² ) flip-chip daisy chains with 10k and 100k bumps maintained high Nb critical current post-bonding (> 50 mA), demonstrating a viable platform for building larger superconducting computing systems.

Reticle

Image stitching

Photomask

Critical dimension

10.1109/ectc32862.2020.00097

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Citations (7)

Electrical Control of near-Field Energy Transfer between Quantum Dots and Two-Dimensional Semiconductors

Nano Letters (2015)

Dhiraj Prasai Andrey R. Klots A. K. M. Newaz J. Scott Niezgoda Noah J. Orfield

We investigate near-field energy transfer between chemically synthesized quantum dots (QDs) and two-dimensional semiconductors. We fabricate devices in which electrostatically gated semiconducting monolayer molybdenum disulfide (MoS2) is placed atop a homogenous self-assembled layer of core-shell CdSSe QDs. We demonstrate efficient non-radiative F\"orster resonant energy transfer (FRET) from QDs into MoS2 and prove that modest gate-induced variation in the excitonic absorption of MoS2 lead to large (~500%) changes in the FRET rate. This, in turn, allows for up to ~75% electrical modulation of QD photoluminescence intensity. The hybrid QD/MoS2 devices operate within a small voltage range, allow for continuous modification of the QD photoluminescence intensity, and can be used for selective tuning of QDs emitting in the visible-IR range.

Molybdenum disulfide

10.1021/acs.nanolett.5b00514

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Citations (116)

Analysis of Multilayer Devices for Superconducting Electronics by High-Resolution Scanning Transmission Electron Microscopy and Energy Dispersive Spectroscopy

IEEE Transactions on Applied Superconductivity (2017)

Nancy A. Missert Paul G. Kotula Michael J. Rye Laura Rehm Volker Sluka

A focused ion beam was used to obtain cross-sectional specimens from both magnetic multilayer and Nb/Al-AlOx/Nb Josephson junction devices for characterization by scanning transmission electron microscopy (STEM) and energy dispersive X-ray spectroscopy (EDX). Automated multivariate statistical analysis of the EDX spectral images produced chemically unique component images of individual layers within the multilayer structures. STEM imaging elucidated distinct variations in film morphology, interface quality, and/or etch artifacts that could be correlated to magnetic and/or electrical properties measured on the same devices.

Energy-dispersive X-ray spectroscopy

Electron spectroscopy

10.1109/tasc.2017.2669579

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Citations (5)

Superconductor Electronics Fabrication Process with MoNx Kinetic Inductors and Self-Shunted Josephson Junctions

IEEE Transactions on Applied Superconductivity (2018)

Sergey K. Tolpygo Vladimir Bolkhovsky D.E. Oates Ravi Rastogi Scott Zarr

Recent progress in superconductor electronics fabrication has enabled single-flux-quantum (SFQ) digital circuits with close to one million Josephson junctions (JJs) on 1-cm$^2$ chips. Increasing the integration scale further is challenging because of the large area of SFQ logic cells, mainly determined by the area of resistively shunted Nb/AlO$_x$-Al/Nb JJs and geometrical inductors utilizing multiple layers of Nb. To overcome these challenges, we are developing a fabrication process with self-shunted high-J$_c$ JJs and compact thin-film MoN$_x$ kinetic inductors instead of geometrical inductors. We present fabrication details and properties of MoN$_x$ films with a wide range of T$_c$, including residual stress, electrical resistivity, critical current, and magnetic field penetration depth {\lambda}$_0$. As kinetic inductors, we implemented Mo$_2$N films with T$_c$ about 8 K, {\lambda}$_0$ about 0.51 {\mu}m, and inductance adjustable in the range from 2 to 8 pH/sq. We also present data on fabrication and electrical characterization of Nb-based self-shunted JJs with AlO$_x$ tunnel barriers and J$_c$ = 0.6 mA/{\mu}m$^2$, and with 10-nm thick Si$_{1-x}$Nb$_x$ barriers, with x from 0.03 to 0.15, fabricated on 200-mm wafers by co-sputtering. We demonstrate that the electron transport mechanism in Si$_{1-x}$Nb$_x$ barriers at x < 0.08 is inelastic resonant tunneling via chains of multiple localized states. At larger x, their Josephson characteristics are strongly dependent on x and residual stress in Nb electrodes, and in general are inferior to AlO$_x$ tunnel barriers.

Kinetic inductance

10.1109/tasc.2018.2809442

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Citations (50)