Rinus T. P. Lee

GlobalFoundries (Germany)

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Yee‐Chia Yeo

Taiwan Semiconductor Manufacturing Company (Taiwan)

Ganesh S. Samudra

National University of Singapore

Tsung-Yang Liow

Agency for Science, Technology and Research

Kian-Ming Tan

National University of Singapore

Andy Eu-Jin Lim

CSIRO Manufacturing

N. Balasubramanian

University of Groningen

Richard J. Hill

Fermi National Accelerator Laboratory

Guo‐Qiang Lo

Singapore Science Park

Chih-Hang Tung

Taiwan Semiconductor Manufacturing Company (Taiwan)

Mantavya Sinha

National University of Singapore

Cooperative Institutions

National University of Singapore

GlobalFoundries (United States)

Agency for Science, Technology and Research

Institute of Microelectronics

Singapore Science Park

Institute of Materials Research and Engineering

GlobalFoundries (Germany)

IBM (United States)

Applied Materials (United States)

Nanyang Technological University

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Novel Nickel-Alloy Silicides for Source/Drain Contact Resistance Reduction in N-Channel Multiple-Gate Transistors with Sub-35nm Gate Length

International Electron Devices Meeting (2006)

Rinus T. P. Lee Tsung-Yang Liow Kian-Ming Tan Andy Eu-Jin Lim Hoong-Shing Wong

In this work, we examined the Schottky-barrier height modulation of NiSi by the incorporation of aluminum (Al), titanium (Ti), erbium (Er), and ytterbium (Yb) in NiSi to form different NiSi-alloys. Among the NiSi-alloy candidates investigated, it was found that the NiAl-alloy silicide provides the most effective Schottky-barrier height lowering (~250 meV) on n-Si(001) substrates. Integration of NiAl-alloy silicides as the source and drain (S/D) silicide material for multiple-gate transistors (MuGFETs) was explored, and shown to deliver a drive current IDsat enhancement of 34% compared to MuGFETs employing NiSi S/D. We further showed that the novel NiAl-alloy silicidation process is compatible with lattice-mismatched silicon-carbon (SiC) S/D stressors. NiAl-alloy silicide is therefore a promising S/D silicide material for reducing the high parasitic series resistance in narrow fin MuGFETs for enhanced device performance

Contact resistance

Parasitic element

10.1109/iedm.2006.346915

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Citations (21)

A High-Stress Liner Comprising Diamond-Like Carbon (DLC) for Strained p-Channel MOSFET

IEEE Electron Device Letters (2008)

Kian-Ming Tan Ming Zhu Wei-Wei Fang Mingchu Yang Tsung-Yang Liow

We report the integration of a new liner stressor comprising diamond-like carbon (DLC) film over a p-channel transistor. A high compressive stress of 6.5 GPa was achieved in a high-stress film with a thickness of 27 nm. A 74% enhancement in drive current was observed for the strained device with DLC liner as compared to a control device without DLC liner. Due to its much higher intrinsic stress value compared to conventional SiN films, a thinner DLC layer can induce comparable amount of stress in the transistor channel compared to a thicker SiN. The DLC material is a potential next-generation high-stress and low-permittivity liner stressor material suitable for application in transistors with aggressively scaled pitch dimensions.

Diamond-like carbon

Carbon fibers

10.1109/led.2007.914103

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Citations (17)

Advanced Contact Technology for MOSFETs: Integration of New Materials for Series Resistance Reduction

ECS Transactions (2009)

Yee‐Chia Yeo Rinus T. P. Lee

In this paper, new technology solutions for reducing contact resistance to enhance MOSFET drive current performance are discussed. We focus on several new approaches pioneered by our group for reducing electron and hole heights between the heavily-doped diffusion region and the silicide layer in n-FET and p-FET, respectively. Integration of these approaches in advanced device architectures would contribute to realization of high-performance CMOS devices.

Equivalent series resistance

Contact resistance

Realization (probability)

10.1149/1.3203967

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Citations (1)

Effectiveness of Aluminum Incorporation in Nickel Silicide and Nickel Germanide Metal Gates for Work Function Reduction

Extended Abstracts of the 2020 International Conference on Solid State Devices and Materials (2007)

Andy Eu-Jin Lim Rinus T. P. Lee Alvin Tian-Yi Koh Ganesh S. Samudra Dim‐Lee Kwong

In this paper, nickel–aluminum (Ni1-xAlx) alloys were employed for Al incorporation in nickel silicide (NiSi) and nickel germanide (NiGe) metal gates [denoted by Ni(Al)Si and Ni(Al)Ge, respectively] to achieve n-channel metal–oxide–semiconductor (NMOS) work function Φm tunability. A higher annealing temperature during gate formation was found to increase Al concentration at the gate/dielectric interface. The presence of low Φm Al at the gate/dielectric interface reduces the NiSi and NiGe Φm by ~0.2 and ~0.6 eV, respectively. However, the saturation in both Ni(Al)Si and Ni(Al)Ge gate Φm at ~4.4 eV is due to Fermi-pinning from the formation of interfacial Al2O3 which prevented a further lowering in Φm to that of pure Al (~4.1–4.3 eV).

Germanide

10.7567/ssdm.2007.a-9-2

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Germanium Source and Drain Stressors for Ultrathin-Body and Nanowire Field-Effect Transistors

IEEE Electron Device Letters (2008)

Tsung-Yang Liow Kian-Ming Tan Rinus T. P. Lee Ming Zhu Ben Tan

Pure germanium (Ge) source and drain (S/D) stressors are integrated with ultrathin-body (UTB) and nanowire field-effect transistors (FETs). This is the first report of the integration of Ge S/D stressors in FETs. The Ge S/D stressors induce a large compressive stress in the channel, resulting in up to 80% I _Dsat enhancement in UTB-FETs. Electrical results further show that increased substrate compliance effects allow nanowire FETs to achieve even higher levels (96%) of strain-induced enhancement.

Stressor

Strain engineering

10.1109/led.2008.2000669

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Citations (11)

Scaling Challenges for Advanced CMOS Devices

International Journal of High Speed Electronics and Systems (2017)

Ajey P. Jacob Ruilong Xie Min Gyu Sung Lars W. Liebmann Rinus T. P. Lee

The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore’s law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors.

Moore's law

10.1142/s0129156417400018

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Citations (85)

Material and Electrical Characterization of Nickel Germanide for p-channel Germanium Schottky Source/Drain Transistors

Extended Abstracts of the 2020 International Conference on Solid State Devices and Materials (2005)

Rinus T. P. Lee Siao Li Liew Bavani Balakrisnan K.Y. Lee Yee‐Chia Yeo

Germanide

Characterization

Nickel compounds

10.7567/ssdm.2005.c-7-1

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Citations (0)

Silicon: Carbon Source/Drain Stressors: Integration of a Novel Nickel Aluminide-Silicide and Post-Solid-Phase-Epitaxy Anneal for Reduced Schottky-Barrier and Leakage

ECS Transactions (2009)

Shao Ming Koh Wei-Jing Zhou Rinus T. P. Lee Mantavya Sinha Chee-Mang Ng

We report two distinct approaches to reduce leakage and parasitic resistance in Silicon:Carbon (Si:C) region. First, the effectiveness of a low-thermal budget post-Solid-Phase-Epitaxy (post-SPE) anneal in the suppression of leakages is examined. Second, we have developed a novel nickel-aluminide silicide (NiAlSi:C) with dopant-segregation (DS) technology to reduce the Schottky-Barrier height (SBH) for Si:C contacts. An optimum 18% substitutional incorporation of Al in the silicide matrix leads to a 10% reduction in the intrinsic SBH of NiSi:C. A low electron schottky barrier of 0.118 eV was attained with NiAlSi:C contacts on phosphorous-segregated regions. The results on Si:C establish a technique to achieve low leakage, low SBH for low contact resistance and low sheet resistance for Si:C S/D application.

Salicide

Dopant Activation

10.1149/1.3203958

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Citations (4)

Strained p-Channel FinFETs With Extended $\Pi$-Shaped Silicon–Germanium Source and Drain Stressors

IEEE Electron Device Letters (2007)

Kian-Ming Tan Tsung-Yang Liow Rinus T. P. Lee Keat Mun Hoe Chih-Hang Tung

Further enhancement of performance in a strained p-channel multiple-gate or fin field-effect transistor (FinFET) device is demonstrated by utilizing an extended-Pi-shaped SiGe source/drain (S/D) stressor compared to that utilizing only Pi-shaped SiGe S/D. With the usage of a longer hydrofluoric acid cleaning time prior to the selective-epitaxy-raised S/D growth, a recess in the buried oxide is formed. This recess allows the subsequent SiGe growth on the fin sidewalls of the S/D regions to extend into the recessed buried oxide to provide a larger compressive stress in the channel for enhanced electrical performance compared to a device with SiGe S/D stressor. Process simulation shows that longitudinal compressive stress in the channel region is higher in a FinFET with extended-Pi-SiGe S/D than that with Pi-SiGe S/D. An enhancement of 26% in the drive current was experimentally observed, demonstrating further boost in enhancement of strained p-channel FinFET with little additional cost using this novel process.

Silicon-germanium

Fin

10.1109/led.2007.905406

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Citations (30)

Sub-30 nm Strained p-Channel Fin-Type Field-Effect Transistors with Condensed SiGe Source/Drain Stressors

Japanese Journal of Applied Physics (2007)

Kian-Ming Tan Tsung-Yang Liow Rinus T. P. Lee King-Jien Chui Chih-Hang Tung

Strained p-channel fin-type field-effect transistors (FinFETs) with SiGe source and drain (S/D) regions formed by a Ge condensation process is demonstrated. SiGe epitaxial layer was grown on the sidewalls at the S/D regions after a successful removal of both the polysilicon gate and nitride spacer stringer. Condensation of the SiGe at the S/D region was subsequently performed. The novel local Ge condensation not only drives Ge into the Si fin and/or increases the Ge concentration in the S/D regions for enhanced strain effects, but also eliminates the need for S/D recess etch, leading to process simplicity. Compared to a FinFET with uncondensed Si1-xGex S/D, FinFETs with condensed Si1-yGey S/D exhibit 28% higher drive current. Devices with gate lengths down to 26 nm were demonstrated with excellent control of short-channel effects.

Fin

10.1143/jjap.46.2058

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Citations (9)