Magdy Bayoumi

University of Louisiana at Lafayette

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Kasem Khalil

University of Mississippi

Mohamed El‐Gamel

Mansoura University

Mahmoud Darwich

University of Mount Union

Ahmed Abdelgawad

Central Michigan University

Dmitri Perkins

University of Louisiana at Lafayette

Yasser Ismail

National Guard Health Affairs

Ashok Kumar

University of Louisiana at Lafayette

Haytham Idriss

Purdue University Fort Wayne

W. Badawy

Egyptian Russian University

Bappaditya Dey

IMEC

Cooperative Institutions

University of Louisiana at Lafayette

217

Park University

104

Chinese Academy of Sciences

Sewanee: The University of the South

University of Illinois Urbana-Champaign

Weatherford College

Institute of Electrical and Electronics Engineers

Intel (United States)

Shanghai Jiao Tong University

University of Missouri

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Low-power and high-speed architecture for EBCOT block in JPEG2000 system

R.E. Aly Magdy Bayoumi

In this paper we propose a novel low power and high-speed architecture for the context formation sub block in tier-1 block of JPEG2000 system. The proposed architecture is inspired from the statistical analysis results on 20 images with 512*512 bits each. The behavior of the proposed architecture is compared to the speedy architecture proposed. For code block size of 64*64 bits, the timing and power consumption analysis show that the proposed architecture can reduce the power consumption by approximately 21% and increase the processing speed by approximately 46% with respect to the reference architecture.

JPEG 2000

Block size

10.1109/mwscas.2004.1354394

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RFID Security : A Lightweight Paradigm

Ahmed Khattab Zahra Jeddi Esmaeil Amini Magdy Bayoumi

This book provides a comprehensive treatment of security in the widely adopted, Radio Frequency Identification (RFID) technology. The authors present the fundamental principles of RFID cryptography in a manner accessible to a broad range of readers, enabling them to improve their RFID security design. This book also offers the reader a range of interesting topics portraying the current state-of-the-art in RFID technology and how it can be integrated with todays Internet of Things (IoT) vision. The authors describe a first-of-its-kind, lightweight symmetric authenticated encryption cipher called Redundant Bit Security (RBS), which enables significant, multi-faceted performance improvements compared to existing cryptosystems. This book is a must-read for anyone aiming to overcome the constraints of practical implementation in RFID security technologies.

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Deep Learning based Defect classification and detection in SEM images: A Mask R-CNN approach

arXiv (Cornell University) (2022)

Bappaditya Dey Enrique Dehaerne Kasem Khalil Sandip Halder Philippe Leray

In this research work, we have demonstrated the application of Mask-RCNN (Regional Convolutional Neural Network), a deep-learning algorithm for computer vision and specifically object detection, to semiconductor defect inspection domain. Stochastic defect detection and classification during semiconductor manufacturing has grown to be a challenging task as we continuously shrink circuit pattern dimensions (e.g., for pitches less than 32 nm). Defect inspection and analysis by state-of-the-art optical and e-beam inspection tools is generally driven by some rule-based techniques, which in turn often causes to misclassification and thereby necessitating human expert intervention. In this work, we have revisited and extended our previous deep learning-based defect classification and detection method towards improved defect instance segmentation in SEM images with precise extent of defect as well as generating a mask for each defect category/instance. This also enables to extract and calibrate each segmented mask and quantify the pixels that make up each mask, which in turn enables us to count each categorical defect instances as well as to calculate the surface area in terms of pixels. We are aiming at detecting and segmenting different types of inter-class stochastic defect patterns such as bridge, break, and line collapse as well as to differentiate accurately between intra-class multi-categorical defect bridge scenarios (as thin/single/multi-line/horizontal/non-horizontal) for aggressive pitches as well as thin resists (High NA applications). Our proposed approach demonstrates its effectiveness both quantitatively and qualitatively.

Categorical variable

Semiconductor device fabrication

Visual inspection

10.48550/arxiv.2211.02185

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A high speed architecture for MAP decoder

M. Elassal Magdy Bayoumi

In this paper, a new high speed MAP decoder architecture is presented. The speed in the MAP decoder is limited by the recursive iteration loop which updates the state metrics. Lookahead transformation technique alleviates the limitation of the recursive loop by expanding it in time. The focus in this paper is on the design of MAP decoder architecture based on lookahead transformation. One level of lookahead is applied that can process two updating trellis iterations at the same time. Resulting in improving the throughput and reducing the state metric memory. This technique is limited by the increased complexity of the add-compare-select-add (ACSA) unit. Design of less complex ACSA is presented, also the MAP decoder based on the look-ahead is prototyped on Xilinx FPGA.

Trellis (graph)

Soft-decision decoder

Speedup

10.1109/sips.2002.1049687

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Citations (3)

A novel scheduling-based CAD methodology for exploring the design space for low power

Ashok Kumar Magdy Bayoumi

This paper describes a novel approach to scheduling with multiple supply voltages in the high-level synthesis. The proposed approach considers, identifies, and exploits the maximal parallelism available in an initial schedule, and applies a modified stochastic evolution mechanism to iteratively improve, or re-schedule, the previously obtained best-schedule to reduce the maximal power consumption of function-units. Based on simulation and evaluation of the proposed approach (using standard benchmarks), it is observed that a power saving of upto 80% is possible when three supply voltage levels, 5 V, 3.3 V, and 2.4 V are considered. In addition to scheduling for low power, the proposed methodology can serve as a vital guiding tool to a designer for studying the efficacy of different design choices before a final design option is selected.

Design space exploration

10.1109/apccas.1998.743790

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Citations (1)

Formal design of RNS processors

Khaled Elleithy Magdy Bayoumi

A formal design methodology is used to design a residue Number System (RNS) processor. An optimal architecture for the residue decoding process is obtained through this design approach. The architecture is modular, consists of simple cells, and is general for any set of moduli.< >

Residue number system

Process design

Residue (chemistry)

10.1109/ciccas.1991.184429

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Efficient Epileptic Seizure Type Classification Using Hyperdimensional Computing

2022 IEEE Biomedical Circuits and Systems Conference (BioCAS) (2024)

Seyedeh Newsha Estiri Hisham Daoud M. Hassan Najafi Magdy Bayoumi

Epileptic seizure

10.1109/biocas61083.2024.10798217

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An application-specific array architecture for feedforward with backpropagation ANNs

Qutaibah Malluhi Magdy Bayoumi T.R.N. Rao

An application-specific array architecture for Artificial Neural Networks (ANNs) computation is proposed. This array is configured as a mesh-of-appendixed-trees (MAT). Algorithms to implement both the recall and the training phases of the multilayer feedforward with backpropagation ANN model are developed on MAT. The proposed MAT architecture requires only O(log N) time, while other reported techniques offer O(N) time, where N is the size of the largest layer. Beside the high speed performance, pipelining of more than one input pattern can be achieved which further improves the performance.< >

Backpropagation

Feed forward

Feedforward neural network

Rprop

10.1109/asap.1993.397156

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Citations (3)

Resource-Aware Data Fusion Algorithms for Wireless Sensor Networks

Lecture notes in electrical engineering (2012)

Ahmed Abdelgawad Magdy Bayoumi

Sensor Fusion

10.1007/978-1-4614-1350-9

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Citations (55)

A new low power building block cell for adders

Ahmed Sayed Magdy Bayoumi

One of the main factors in developing low power systems is reducing power consumption at the circuit design level and the module building block levels in the design. Following this strategy a low power and high speed full adder cell with the minimum number of transistors has been developed. The proposed cell is a combination of a 3-input XOR gate and transmission gates. The proposed cell has been compared to the other three basic common cells. An extensive analysis of the four architectures of adders, namely carry ripple, carry skip, carry select and carry lookahead has proved the superiority of the proposed cell.

Carry (investment)

Transistor count

Carry-save adder

Serial binary adder

Transmission gate

10.1109/mwscas.1997.662200

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Citations (3)