We discuss the degradation mechanisms of C-doped 0.15-μm gate AlGaN/GaN HEMTs tested by drain step-stress experiments. Experimental results show that these devices exhibit cumulative degradation effects during the step stress experiments in terms of either (i) transconductance (gm) decrease without any threshold-voltage (VT) change under OFF-state stress, or (ii) both VT and gm decrease under ON-state stress conditions. To aid the interpretation of the experiments, two-dimensional hydrodynamic device simulations were carried out. Based on obtained results, we attribute the gm decrease accumulating under OFF-state stress to hole emission from CN acceptor traps in the gate-drain access region of the buffer, resulting in an increase in the drain access resistance. On the other hand, under ON-state stress, channel hot electrons are suggested to be injected into the buffer under the gate and in the gate-drain region where they can be captured by CN traps, leading to VT and gm degradation, respectively.
Atomistic density functional theory (DFT) calculations of the capacitance between a metallic cylindric gate and a carbon nanotube (CNT) are reported. Results stressing the predominant effect of quantum capacitance in limiting or even enhancing screening properties of the CNT are shown. Other contributions to the quantum capacitance beyond the electronic density of state (DOS) are pointed out. Negative values of the quantum capacitance are obtained for low-density systems, which correspondingly over-screen the gate field. This unconventional behavior of the quantum capacitance is related to the predominance of the exchange contribution in the total electronic energy of the CNT.
We report density-functional theory (DFT), atomistic simulations of the non-equilibrium transport properties of carbon nanotube (CNT) field-effect transistors (FETs). Results have been obtained within a self-consistent approach based on the non-equilibrium Green's functions (NEGF) scheme. Our attention has been focused on a new kind of devices, the so called bulk-modulated CNTFETs. Recent experimental realizations \cite{Chen,Lin_condMat} have shown that such devices can exhibit excellent performances, even better than state-of-the-art Schottky barrier (SB)-modulated transistors. Our calculations have been intended to explore, at an atomistic level, the physical mechanisms governing the transport in these new devices. We emphasize the role that one-dimensional screening has on gate- and drain-induced current modulation mechanisms, pointing out, at the same time, the importance of a correct evaluation of the nanotube quantum capacitance. The operative regimes and the performance limits of the device are analysed, pointing out, at the same time, the role played by the quasi-one-dimensional, short channel effects.
We report density-functional theory (DFT) atomistic simulations of the nonequilibrium transport properties of carbon nanotube (CNT) field-effect transistors (FETs). Results have been obtained within a self-consistent approach based on the nonequilibrium Green's functions (NEGF) scheme. We show that, as the current modulation mechanism is based on the local screening properties of the nanotube channel, a completely new, negative quantum capacitance regime can be entered by the device. We show how a well-tempered device design can be accomplished in this regime by choosing suitable doping profiles and gate contact parameters. At the same time, we detail the fundamental physical mechanisms underlying the bulk-switching operation, including them in a very practical and accurate model, whose parameters can be easily controlled in order to improve the device performance. The dependence of the nanotube screening properties on the temperature is finally explained by means of a self-consistent temperature analysis
Localized strained silicon was observed with a suitable resolution in a real semiconductor device by tip-enhanced Raman spectroscopy (TERS). The device was made via a standard industrial process and its silicon trench isolation structures were used for the silicon strain analysis obtaining results according to finite element method-based simulation data. We have achieved a reliable and repeatable enhancement factor obtaining a trace of strained silicon along the structure with suitable nanometer spatial resolution compatible with IC industry requirements. We demonstrate that the complexity to analyze a real 3D structure, directly from the production lines and not ad hoc realized, entails the challenges to individuate the optimal tip shape, tip contact angle, tip composition, tip positioning system, laser power, and wavelength to achieve an appropriate plasmon resonance inducing a relevant signal to noise ratio. This work gives the base to address the development in TERS optimization for real industrial applications.
The aim of Molecular and Nano Electronics: Analysis, Design and Simulation is to draw together contributions from some of the most active researchers in this new field in order to illustrate a theory guided-approach to the design of molecular and nano-electronics. The field of molecular and nano-electronics has driven solutions for a post microelectronics era, where microelectronics dominate through the use of silicon as the preferred material and photo-lithography as the fabrication technique to build binary devices (transistors). The construction of such devices yields gates that are able to perform Boolean operations and can be combined with computational systems, capable of storing, processing, and transmitting digital signals encoded as electron currents and charges. Since the invention of the integrated circuits, microelectronics has reached increasing performances by decreasing strategically the size of its devices and systems, an approach known as scaling-down, which simultaneously allow the devices to operate at higher speeds.
In the last years a lot of effort has been directed in order to reduce ion implantation damage, which can be detrimental for silicon device performances. Implantation's dose rate and temperature were found to be two important factors to modulate residual damage left in silicon after anneal. In this work high dose rate, low temperature, high dose arsenic and boron implantations are compared to the corresponding low dose rate, room temperature processes in terms of silicon lattice defectiveness and dopant distribution, before and after anneal is performed. The considered implant processes are the one typically used to form a source/drain region in a CMOS process flow in the submicron technology node. A spike anneal process was applied to activate the dopant. Low temperature, high dose rate implantations have found to be effective in reducing silicon extended defects with a negligible effect on the profile of the activated dopant. Experimental set up, results and possible explanation will be reported and discussed in the paper.
