We analyze the performance of two different real-time operating systems. Therefore, we used a real benchmark embedded system design with fast external reaction times of about 220 /spl mu/s. We show that for such fast reactive systems, the software overhead of a real-time operating system becomes a limiting factor. We analyze the influence of novel microcontroller features, e.g., different on-chip caches, which tend to accelerate execution, but make it less predictable. These investigations have been conducted using our own emulation environment called SPYDER-CORE-P1.
This paper presents a new approach to the design of embedded systems. Due to restrictions that state-of-the-art methodologies contain for hardware/software partitioning, we have developed an emulation based method using the facilities of reconfigurable hardware components, such as field programmable gate arrays (FPGA). Our own emulation environment called the SPYDER tool set was used; it is best suited for the emulation of hardware designs for embedded systems.
Article Free AccessExploiting FPGA-features during the emulation of a fast reactive embedded system Share on Authors: Karlheinz Weiß University of Tübingen, Technical Computer Science, Sand 13, D-72076 Tübingen, Germany University of Tübingen, Technical Computer Science, Sand 13, D-72076 Tübingen, GermanyView Profile , Thorsten Steckstor University of Tübingen, Technical Computer Science, Sand 13, D-72076 Tübingen, Germany University of Tübingen, Technical Computer Science, Sand 13, D-72076 Tübingen, GermanyView Profile , Gernot Koch University of Tübingen, Technical Computer Science, Sand 13, D-72076 Tübingen, Germany University of Tübingen, Technical Computer Science, Sand 13, D-72076 Tübingen, GermanyView Profile , Wolfgang Rosenstiel University of Tübingen, Technical Computer Science, Sand 13, D-72076 Tübingen, Germany University of Tübingen, Technical Computer Science, Sand 13, D-72076 Tübingen, GermanyView Profile Authors Info & Claims FPGA '99: Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arraysFebruary 1999 Pages 235–242https://doi.org/10.1145/296399.296469Online:01 February 1999Publication History 3citation367DownloadsMetricsTotal Citations3Total Downloads367Last 12 Months2Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF
This paper presents the power consumption estimation for the novel Virtex architecture. Due to the fact that the XC4000 and the Virtex core architecture are very similar, we used the basic approaches for the XC4000-FPGAs power consumption estimation and extended that method for the new Virtex family. We determined an appropriate technology-dependent power factor Kp to calculate the power consumption on Virtex-chips, and developed a special benchmark test design to conduct our investigations. Additionally, the derived formulas are evaluated on two typical industrial designs. Our own emulation environments called SPYDER-ASIC-X1 and SPYDER-VIRTEX-X2 were used, which are best suited for the emulation of hardware designs for embedded systems.
