Andy Tseng

ON Semiconductor (United States)

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Yi‐Shao Lai

Advanced Semiconductor Engineering (Taiwan)

Bernd K. Appelt

Evans Analytical Group (United States)

Louie Huang

Advanced Semiconductor Engineering (Taiwan)

William T. Chen

Evans Analytical Group (United States)

Curtis Chen

Advanced Semiconductor Engineering (Taiwan)

Bill Liu

Institute of Astronomy and Astrophysics, Academia Sinica

Winnie Tai

Advanced Semiconductor Engineering (Taiwan)

Shingo Itoh

Kansai University

Ping Chen

Dalian University of Technology

Nicholas Liao

Georgia Institute of Technology

Cooperative Institutions

Advanced Semiconductor Engineering (Taiwan)

Sumitomo Bakelite (Japan)

Centre National de la Recherche Scientifique

Cornell University

Karlsruhe Institute of Technology

Laboratoire d'Informatique de Grenoble

Institut polytechnique de Grenoble

Université Grenoble Alpes

Université Joseph Fourier

National Sun Yat-sen University

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Opportunities for the Application of Fracture Mechanics in Microelectronic Packaging

Proceedings of the Asian Pacific Conference on Fracture and Strength and International Conference on Advanced Technology in Experimental Mechanics (2001)

William T. Chen Andy Tseng J.E. Hayward Ming Li

The electronic industry is the largest manufacturing industry in the world.It is an industry, which employs a large number of engineers and scientists working in design, development and manufacturing where materials and mechanics are regularly utilized as part of their professional portfolio.The power and dynamism of the electronic industry depend to a great extent upon the exponential growth in speed and function of the semiconductors and their utilization in computers, telecommunication, aerospace, automotive, entertainment, consumer products, and in fact all fabrics of our society.

Microelectronics

10.1299/jsmeatemapcfs.1.01.203.0_40

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Copper wire bonding experiences from a manufacturing perspective

Bernd K. Appelt Andy Tseng Yi‐Shao Lai

The rapid ramping of fine pitch copper wire bonding production is a perfect example of a market driven technology implementation. The explosive increase in gold commodity pricing has paved the road for this conversion. Several challenges known from thick copper wire bonding had to be overcome to make this technology viable technically and economically. Some fundamental studies of copper wire bonding to the full spectrum of die surfaces and wafer nodes was available at the beginning of manufacturing implementation but over the last year, a large number of research papers have been published greatly enhancing the basic understanding of mechanism, metallurgy and chemistry of copper wire bonding. Equipment manufacturers have developed dedicated copper wire bonders and tool kits, wire manufacturers have developed softer copper wires as well as oxidation resistant wires, mold compound suppliers have developed low corrosion compounds and wire bond engineers have learned to optimize the bonding process to yield cost effective and reliable copper wire bond die packages. Here, high volume manufacturing experiences of copper wire bond packaging and long term reliability data will be presented.

Wire bonding

Copper wire

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Citations (3)

Advanced QFN packaging for low cost and solution

Bill C.J.Bruce Hu Mark W. Lin Timmy Lin Sunny Lee

The advanced QFN (aQFN) package is an enhanced version of conventional QFN (Quad Flat No-Lead) with multiple row terminals of featuring higher number of I/O ports. aQFN thermal and electrical performance are superior due to smaller profile, shorter interconnects. Also, the solder wettability control and board-level thermo-mechanical reliability are greatly enhanced over conventional QFN because of the higher package standoff. aQFN provides similar I/O number approaching that of a BGA-type chip-scale package (CSP) but much less cost since the expensive substrate is replaced by lead frame. aQFN turns out to be an ideal low cost solution for electrical components of portable telecommunication applications. With such advantages, the replacement of BGA-type CSP with aQFN from low pin-count up to medium high pin-count applications is therefore highly expectable, especially for handheld & PDA devices with its relative applications. In this paper, aQFN is introduced in terms of its application advantages, development, fabrication process flow, SMT process with stencil design guideline. The simulation results indicate that thermal and electrical performances of aQFN are much better than BGA-type CSP, when the same functions are to be designed in SMT process.

Ball grid array

Lead frame

Chip-scale package

Stencil

Integrated circuit packaging

Package on package

Electronic Packaging

Temperature cycling

10.1109/icept.2010.5582373

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Citations (15)

Comparison of advanced measurement and modeling techniques for electrical characterization of ball grid array packages

Tzyy‐Sheng Horng Andy Tseng Hui‐Hsun Huang Shujing Wu Jinhyun Lee

Advanced measurement and modeling techniques are proposed in both the frequency domain and time domain to establish the high-frequency/high-speed equivalent models of Ball Grid Array (BGA) packages. In consideration of the adjacent coupled traces of the packages, the electrical parameters that are found include characteristic impedance, coupling coefficient, and propagation delay for the equivalent coupled transmission-line models, and self inductance, mutual inductance, loaded capacitance, and mutual capacitance for the equivalent lump models.

Ball grid array

Equivalent series inductance

Equivalent impedance transforms

LCR meter

10.1109/ectc.1998.678938

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Citations (10)

Copper Wire Bonding in High Volume Manufacturing

ECS Transactions (2011)

Bernd K. Appelt Andy Tseng Yi‐Shao Lai Chun‐Hsiung Chen

Wire bonding is still by far the dominant interconnection technology with about 90% market share. Copper wire bonding has achieved approximately 15% penetration within two years. Considerable amount of fundamental characterization has been performed to understand the nature of Cu wire bonding and even more analysis has been done in manufacturing to ensure reliable packages can be shipped. Here, some of the methodology of successful, high volume manufacturing will be described. Rigorous process optimization and product characterization are key and will be detailed. Supportive data from extended reliability testing demonstrates that 2 x the standard JEDEC life can be achieved. This is in part due to the very slow intermetallic growth rate and in part due to the proper choice of mold compound. The other elements are strict adherence and control of bonding parameters and rigorous clean room management which is also reflected in yields being equivalent to gold wire bonding.

Wire bonding

Characterization

10.1149/1.3567683

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Citations (2)

Defect Healing of Carbon Nanotubes by Rapid Vacuum Arc Annealing

MRS Proceedings (2007)

Jeff T. H. Tsai Jason Li Andy Tseng

Electric arc

10.1557/proc-1057-ii10-31

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Citations (2)

Quaero at TRECVID 2010: Semantic Indexing

HAL (Le Centre pour la Communication Scientifique Directe) (2010)

Stéphane Ayache Bahjat Safadi Andy Tseng Franck Thollard Georges Quénot

Source

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Fine Pitch Cu Wire Bonding – As Good As Gold

IMAPSource Proceedings (2010)

Bernd K. Appelt William T. Chen Andy Tseng Yi‐Shao Lai

Fine pitch wire bonding has traditionally been the domain of gold wires. The significant increase in gold commodity prices has driven a continuous reduction in wire diameters to minimize the impact of the raw materials cost of the wire. This has reached a point now where copper wires are beginning to displace gold wires despite the technical challenges associated with copper wires. The basic challenges like propensity for oxidation, hardness and propensity for corrosion can be managed with the appropriate investment in tooling and infrastructure. Doubts are persisting about yield and reliability. With a very methodical approach to developing the process controls, it can be demonstrated that yields are as good as those for gold despite the fact that copper bonds are not reworkable. Likewise, the typical JEDEC reliability tests can be full filled. Here, an extensive effort has been placed on extended JEDEC testing to demonstrate that with good process control and proper materials choices, test durations of more than 2x can be passed. This excellent performance demonstrates that copper wire bonding can be as good as or better than gold wire bonding.

Wire bonding

Copper wire

10.4071/isom-2010-wp4-paper1

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Citations (2)

Overview of recent developments in microelectronic packaging

W.T. Chen Andy Tseng

This presentation will review recent developments and future challenges in microelectronic packaging. The increase in transistor density per each generation of semiconductor technology results in demands for corresponding increase for packaging interconnection density. In meeting these demands there has been a continuous stream of new innovations and new developments in all aspects of microelectronic packaging: in materials, processing, new designs, reliability and testing, metrology, modeling and simulation.

Microelectronics

Integrated circuit packaging

Presentation (obstetrics)

Electronic Packaging

10.1109/emap.2001.983949

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Citations (8)

Thin packaging - What is next?

Bernd K. Appelt Andy Tseng Shoji Uegaki Kay S Essig

The drive for miniaturization of electronic packaging is continuing relentlessly due to ever more functionality in smaller, lighter mobile products. Consequently, innovations are required in packaging technology, and more importantly, in enabled volume manufacturing. Some recent trends in thin products and packaging will be high-lighted and compared to the JEDEC standards for packages. The ASE roadmaps for package size reductions will be presented with particular focus on prepreg based substrate technology. A single sided substrate has been developed and is currently shipping in high volume. The manufacturing concept for this substrate has been adapted to build coreless substrates based on prepreg which are currently in characterization. Further adaptation has led to embedded component, actives and passives, substrates which are currently in qualification. For the later, a new manufacturing form factor has been chosen to take advantage of the assembly infrastructure and to maximize the yield of the substrate which is a key factor for the commercial success of this technology. ASE is offering these substrates in full turnkey service from wafer sort to bumping to embedding in the substrate to assembly of top components, balling and final test.

Wafer-level packaging

Bumping

Electronic Packaging

10.1109/icsj.2012.6523400

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Citations (1)