D.C. Dhubkarya

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Deepak Nagariya

Jay Kumar

Dalhousie University

Deepak Nagaria

Bundelkhand University

Richa Kapoor

Anand Agricultural University

Rakesh Kapoor

Sanjay Gandhi Post Graduate Institute of Medical Sciences

Cooperative Institutions

Dalhousie University

University of Electronic Science and Technology of China

Huzhou University

Lovely Professional University

Chandigarh University

University of California, Davis

Rajasthan Technical University

Quaid-i-Azam University

University of Kota

Dr. Bhim Rao Ambedkar University

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Implementation of a Radial Basis Function Using VHDL

Global Journal of Computer Science and Technology (2010)

Richa Kapoor D.C. Dhubkarya Deepak Nagaria

This paper presents the work regarding the implementation of neural network using radial basis function algorithm on very high speed integrated circuit hardware description language (VHDL). It is a digital implementation of neural network. Neural Network hardware has undergone rapid development during the last decade. Unlike the conventional von-Neumann architecture that is sequential in nature, Artificial Neural Networks (ANNs) Profit from massively parallel processing. A large variety of hardware has been designed to exploit the inherent parallelism of the neural network models. The radial basis function (RBF) network is a two-layer network whose output units form a linear combination of the basis function computed by the hidden unit and hidden unit function is a Gaussian. The radial basis function has a maximum of 1 when its input is 0. As the distance between weight vector and input decreases, the output increases. Thus, a radial basis neuron acts as a detector that produces 1 whenever the input is identical to its weight vector.

Basis (linear algebra)

Activation function

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A Comparative Study of Different Learning Rate In Radial Basis Function

International Conference on Computational Intelligence and Communication Networks (2010)

Rakesh Kapoor Jay Kumar D.C. Dhubkarya Deepak Nagariya

This paper presents the work regarding the implementation of radial basis function algorithm on very high speed integrated circuit hardware description language by using Perceptron learning. Neural Network hardware is usually defined as those devices designed to implement neural architectures and learning algorithms. The radial basis function (RBF) network is a two-layer network whose output units form a linear combination of the basis function computed by the hidden unit & hidden unit function is a Gaussian. The radial basis function has a maximum of 1 when its input is 0. As the distance between weight vector and input decreases, the output increases. Thus, a radial basis neuron acts as a detector that produces 1 whenever the input is identical to its weight vector.

Basis (linear algebra)

Perceptron

Activation function

Basis function

10.1109/cicn.2010.121

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Function Optimization Using Genetic Algorithm By VHDL

Global Journal of Computer Science and Technology (2010)

D.C. Dhubkarya Deepak Nagariya Jay Kumar

This paper presents the work regarding the synthesis and implementation of a hardware genetic algorithm utilizing very high speed integrated circuit hardware description language (VHDL) for programming FPGAs. Genetic Algorithms were invented to mimic some of the processes observed in natural evolution. The idea with GA is to use this power of evolution to solve optimization problems. They are based on the principles of the evolution via natural selection, employing a population of individuals that undergo selection in the presence of variation-inducing operators such as mutation and recombination (crossover). we solved the problem with the help of hardware description language so it’s take less time to find a result as compare to GA’s because of HDL solve the problem by parallel processing. The present work deals with implementation and optimization of De jong’s first function. Genetic algorithms need large memory banks to store the intermediate results and this has made the hardware implementation of GAs very inefficient but by using FPGA our task become simpler. Field-Programmable Gate Arrays (FPGAs) are flexible circuits that can be easily reconfigured by the designer. The program is written in VHDL and compiled with 32-Bit Microsoft Windows and implemented on a Spartan-3A FPGA from Xilinx.

Gate array

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