Yasser S. Abdalla

Suez University

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Sherif M. Sharroush

Port Said University

Ahmed A. S. Dessouki

Port Said University

El‐Sayed A. El‐Badawy

Alexandria University

Ammar Armghan

Al Jouf University

Anis R. Boudabbous

Al Jouf University

Sherif F. Nafea

Suez Canal University

Mohamed A. Sharaf

Al Jouf University

M.I. Elmasry

Arab Academy for Science, Technology, and Maritime Transport

Hammad Armghan

Tsinghua University

Amged S. El-Wakeel

Military Technical College

Cooperative Institutions

Port Said University

Suez Canal University

Alexandria University

Military Technical College

Al Jouf University

COMSATS University Islamabad

Suez University

International Islamic University, Islamabad

Helwan University

Al-Azhar University

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Impact of technology scaling on the performance of domino CMOS logic

International Conference on Electronic Design (2008)

Sherif M. Sharroush Yasser S. Abdalla Ahmed A. S. Dessouki El‐Sayed A. El‐Badawy

Domino CMOS logic circuit family finds a wide variety of applications in microprocessors, digital signal processors, and dynamic memory due to their high speed and low device count. However, there are inevitable problems that degrade the noise immunity of this family; they are the inevitable leakage current and the charge sharing. Added to the drawbacks is the relatively large power consumption, especially if compared to the static complementary CMOS logic family. To make the matter worse, these drawbacks are more tactile with the scaling of CMOS technology from one generation to the next. In this paper, the impact of CMOS technology scaling on the performance of domino CMOS logic will be investigated. Specifically, the need to decrease the dynamic power consumption forces the designer to use a lower power-supply voltage. This in turn necessitates the reduction of threshold voltage to maintain the performance with the associated increase in subthreshold leakage current. So, a properly sized PMOS keeper must be used to compensate for this leakage. It will be found that the speed, which is the major advantage of domino logic compared to other logic styles, will degrade with CMOS technology scaling due to the contention current of the keeper. A technique that extends the life time of domino logic in spite of CMOS technology scaling will be proposed. In fact, this technique aims to alleviate the effects of threshold-voltage reduction and the associated increase in subthreshold leakage on the noise immunity and the size of the PMOS keeper through the use of a current sensing circuit. This technique will be simulated for the 0.13 mum technology with power-supply voltage, V _DD =1.2 V. Simulation results show that the proposed technique enhances the noise margin by approximately 560 mV and enhances the speed by approximately 56% compared to the conventional technique in which the gate of the PMOS keeper is connected to the output terminal, however, at the cost of an area penalty.

Domino logic

Subthreshold conduction

Domino

Leakage (economics)

Noise margin

10.1109/iced.2008.4786755

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Citations (15)

Speeding-up wide-fan in domino logic using a controlled strong PMOS keeper

International Conference on Computer and Communication Engineering (2008)

Sherif M. Sharroush Yasser S. Abdalla Ahmed A. S. Dessouki El‐Sayed A. El‐Badawy

Wide fan in domino logic finds a variety of applications in microprocessors, digital signal processors, and dynamic memory. Specifically, there is a large number of applications that contain 8 or more transistors connected in parallel in the pull-down network (PDN) and thus the subthreshold leakage and charge sharing become severe. So, a strong PMOS keeper must be used in order to compensate for this leakage. However, the use of a strong keeper in the conventional domino circuit degrades the speed of the circuit considerably or results in an erroneous output. In this paper, a novel technique that acts to speed up the operation of wide fan in domino logic using a properly sized keeper is proposed. The keeper is controlled via a controlling CMOS circuit. Some design issues of this technique such as the effect of the charge sharing on the operation of the proposed circuit and the size of the PMOS keeper will be discussed in this paper. Simulation will be carried out for the 0.13 mum technology with V _DD =1.2 V for the case of 16 NMOS transistors in the PDN. Simulation results show the better noise immunity of the proposed circuit and the larger speed, however at the cost of increasing the area.

Domino logic

Domino

Fan-in

Charge sharing

Subthreshold conduction

Leakage (economics)

10.1109/iccce.2008.4580681

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Citations (12)

Design of a 3-bit 2.2 ps step 357.5 ps range 0.247 μm2 0.85 μW 45 nm All-MOS delay element

Integration (2024)

Sherif M. Sharroush Yasser S. Abdalla

Delay-locked loop

True time delay

Ring oscillator

10.1016/j.vlsi.2024.102154

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Citations (1)

A Novel Compact and High-Speed CMOS Parity Generator/Checker

Yasser S. Abdalla Sherif M. Sharroush

During the digital transmission of data, the designer is forced to use one of the various methods of data generation and checking, among them is the parity bit. However, CMOS circuits that generate the parity bit (parity generator) and perform the checking operation (parity checking) usually have wide fan-in and thus have a relatively low speed and high power consumption. In this paper, a novel CMOS scheme is presented for the realization of such functions. The proposed scheme is compared with the conventional static CMOS scheme and other schemes. The proposed scheme is verified by simulation using the 45 nm CMOS technology and shows 80.3% and 60% savings in the power-delay product and the area, respectively, assuming eight bits in a single group of data; however, at the expense of more power consumption and less immunity to process, voltage, and temperature (PVT) variations.

Parity (physics)

10.1109/iccisci.2019.8716410

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Citations (1)

An Inversion-Coefficient Based Methodology for Optimizing the Performance of TIAs

Fiber & Integrated Optics (2024)

Aya M. Shaaban Sherif M. Sharroush Yasser S. Abdalla Sherif F. Nafea

The transimpedance amplifier (TIA) can be found in several applications such as optical transceivers, biomedical circuits, and signal-processing circuits. In this paper, an investigation of two widely used transimpedance-amplifier configurations is presented. The two adopted configurations are the regulated cascode-based TIA (RGC-TIA) and the common-source based TIA (CS-TIA) with resistive feedback. These two configurations are studied in the following three inversion regimes; weak, moderate, and strong. A general model for the drain current of the MOSFET transistor, that is valid for all levels of inversion, is adopted. Through the study, the inversion coefficient (IC) of the amplifying device is systematically varied and its impact is investigated on various performance metrics such as gain, bandwidth, noise, distortion, and power consumption. Studying the inversion coefficient is crucial for precisely adjusting the amplifier biasing, thereby enabling the design of enhanced performance TIAs that effectively address the requirements of diverse applications. Compact-form expressions are derived for the performance metrics and compared with the simulation results. A figure of merit incorporating multiple performance metrics is proposed for performing a fair comparison for a wide range of the inversion coefficient. The simulation employs the 130-nm CMOS Predictive Technology Model (PTM) with a power-supply voltage, VDD, equal to 1.2 V.

10.1080/01468030.2024.2429356

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Citations (0)

Introducing the Yasser-map as an improvement of the Karnaugh-map for solving logical problems

Yasser S. Abdalla

This work presents the Yasser-map as an improvement for the Karnaugh-map especially when the number of variables exceeds four. For many years the k-map is considered as the best way for solving logical problems that depend on four variables at most. However, it becomes hard with 5 variables and very difficult with six variables and almost impossible with more than 6 variables. The Quine-McCluskey method used to be the only other choice four such logical problems with large number of variables. However, the Quine-McCluskey method is also complicated and usually it is applied by a computer program. The Yasser-map which is introduced in this work is suitable for problems with low number of variables and also for problems with large number of variables. A six variable example is solved using the Yasser-map to explain how simple it is.

Quine

10.1109/icecct.2015.7226152

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Citations (7)

A novel flash‐like all‐metal‐oxide semiconductor analog‐to‐digital converter suitable for system on chips systems

International Journal of Circuit Theory and Applications (2020)

Yasser S. Abdalla

Summary The analog‐to‐digital converters (ADCs) play a very important role in electronic products, radar, communication systems and signal processing, to name such a few. In this paper, a novel all‐metal‐oxide semiconductor (MOS) flash‐like analog‐to‐digital converter (FLADC) that consists of five stages is proposed. The design was performed using only MOS transistors, and the proposed ADC works in a way similar to the conventional flash ADC. According to the proposed ADC, there is no need for the comparators used in the conventional flash ADCs, thus resulting in a reduction in both the transistor count and the power consumption. The sound operation and the superiority of the proposed ADC compared to previous works is verified by simulation using the 0.13‐μm complementary MOS (CMOS) technology with a power‐supply voltage, V DD , of 1.2 V. The simulation has been conducted on a 5‐bit FLADC that is built by 276 MOS transistors only which is approximately 32% of the transistor count of the corresponding conventional flash ADC and has no resistors. According to the simulation results, the proposed 5‐bit FLADC consumes 3.23 mW at sampling rate of 0.5 GS/s.

Flash ADC

Analog-to-digital converter

Successive approximation ADC

10.1002/cta.2866

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Citations (1)

Two proposed BiCMOS inverters with enhanced performance

Ain Shams Engineering Journal (2023)

Sherif M. Sharroush Yasser S. Abdalla

The BiCMOS technology finds wide applications when driving heavy loads such as those associated with off-chip loads or long runs within the chip. In this paper, two novel BiCMOS inverters that depend on using Darlington BJT pairs are presented. Also, the operation of the two proposed BiCMOS inverters as amplifiers is discussed. We present closed-form analytical expressions for the low-to-high propagation delay, the high-to-low propagation delay, and the inverter-based amplifier parameters such as the gain and bandwidth under arbitrary load capacitance and transistors' parameters. The operation of these two inverters is verified by simulation using the 45 nm CMOS predictive-technology model (PTM) with a power supply voltage, VDD, equal to 1 V. The proposed inverters show superior performance compared with the CMOS inverter, the conventional R-circuit BiCMOS inverter, and the full-swing CMOS/bipolar inverter when driving heavy loads even at low supply voltages.

BiCMOS

10.1016/j.asej.2023.102259

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Far-Field DOA Estimation of Uncorrelated RADAR Signals through Coprime Arrays in Low SNR Regime by Implementing Cuckoo Search Algorithm

Electronics (2022)

Khurram Hameed Wasim Khan Yasser S. Abdalla F. F. Alharbi Ammar Armghan

For the purpose of attaining a high degree of freedom (DOF) for the direction of arrival (DOA) estimations in radar technology, coprime sensor arrays (CSAs) are evaluated in this paper. In addition, the global and local minima of extremely non-linear functions are investigated, aiming to improve DOF. The optimization features of the cuckoo search (CS) algorithm are utilized for DOA estimation of far-field sources in a low signal-to-noise ratio (SNR) environment. The analytical approach of the proposed CSAs, CS and global and local minima in terms of cumulative distribution function (CDF), fitness function and SNR for DOA accuracy are presented. The parameters like root mean square error (RMSE) for frequency distribution, RMSE variability analysis, estimation accuracy, RMSE for CDF, robustness against snapshots and noise and RMSE for Monte Carlo simulation runs are explored for proposed model performance estimation. In conclusion, the proposed DOA estimation in radar technology through CS and CSA achievements are contrasted with existing tools such as particle swarm optimization (PSO).

Cuckoo search

Maxima and minima

Direction of arrival

Robustness

10.3390/electronics11040558

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Citations (7)

Compensating for the keeper current of CMOS domino logic using a well designed NMOS transistor

Sherif M. Sharroush Yasser S. Abdalla Ahmed A. S. Dessouki El‐Sayed A. El‐Badawy

Domino CMOS logic finds a wide variety of applications due to their high speed and low device count. However, this type of logic has the drawback of low noise immunity especially when compared to complementary CMOS logic. This is due to the leakage current and charge sharing. So, a PMOS keeper must be used in order to compensate for this leakage. However, the use of a keeper in the conventional domino circuit degrades the speed of the circuit or results in an erroneous output due to the contention current. In this paper, a novel technique that acts to speed up the operation of domino logic and to improve its noise immunity using a weak keeper is proposed. In this technique, a well designed NMOS transistor will be connected to the dynamic node in order to draw the contention current during the evaluation phase. The term “well designed” will be illustrated through the paper. A modification to the proposed technique will also be presented in which the precharge device need not be increased in size. Simulation will be carried out for the 0.13 µm technology with V DD =1.2 V for the case of AND gate with two inputs. Simulation results show that the speed improves by a factor of approximately 33% and the noise margin increases from only 100 mV to 600 mV in case the dynamic node is to be at logic “0” for the same transistor aspect ratios at the cost of adding only one NMOS transistor and increasing the size of the precharge device, or instead connecting two serially connected NMOS transistors to the dynamic node and keeping the size of the precharge device the same.

Domino logic

Domino

Noise margin

Leakage (economics)

Source

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Citations (6)