A custom Human Activity Recognition system is presented based on the resource-constrained Hardware (HW) implementation of a new partially binarized Hybrid Neural Network. The system processes data in real-time from a single tri-axial accelerometer, and is able to classify between 5 different human activities with an accuracy of 97.5% when the Output Data Rate of the sensor is set to 25 Hz. The new Hybrid Neural Network (HNN) has binary weights (i.e. constrained to +1 or -1) but uses non-binarized activations for some layers. This, in conjunction with a custom pre-processing module, achieves much higher accuracy than Binarized Neural Network. During preprocessing, the measurements are made independent from the spatial orientation of the sensor by exploiting a reference frame transformation. A prototype has been realized in a Xilinx Artix 7 FPGA, and synthesis results have been obtained with TSMC CMOS 65 nm LP HVT and 90 nm standard cells. Best result shows a power consumption of 6.3 μW and an area occupation of 0.2 mm 2 when real-time operations are set, enabling in this way, the possibility to integrate the entire HW accelerator in the auxiliary circuitry that normally equips inertial Micro Electro-Mechanical Systems (MEMS).
In this work, a new custom design of an anomaly detection and classification system is proposed.It is composed of a convolutional Auto-Encoder (AE) hardware design to perform anomaly detection which cooperates with a mixed HW/SW Convolutional Neural Network (CNN) to perform the classification of detected anomalies.The AE features a partial binarization, so that the weights are binarized while the activations, associated to some selected layers, are nonbinarized.This has been necessary to meet the severe area and energy constraints that allow it to be integrated on the same die as the MEMS sensors for which it serves as a neural accelerator.The CNN shares the feature extraction module with the AE, whereas a SW classifier is triggered by the AE when a fault is detected, working asynchronously to it.The AE has been mapped on a Xilinx Artix-7 FPGA, featuring an Output Data Rate (ODR) of 365 kHz and achieving a power dissipation of 333µ W/MHz.Logic synthesis has targeted TSMC CMOS 65 nm, 90 nm, and 130 nm standard cells.Best results achieved highlight a power consumption of 138µ W/MHz with an area occupation of 0.49 mm 2 when real-time operations are set.These results enable the integration of the complete neural accelerator in the CMOS circuitry that typically sits with the inertial MEMS on the same silicon die.Comparisons with the related works suggest that the proposed system is capable of state-of-the-art performances and accuracy.
In this paper, for the first time the design of a HW module to eliminate the effect of the gravity acceleration from data acquired from inertial sensors is presented. A new "hardware friendly" algorithm has been derived from the Rodrigues' rotation formula, which can be implemented in a more compact iterative structure. By exploiting 32-bit floating-point arithmetic, the design is able to combine high accuracy and low power requirements needed by any intelligent Human Activity Recognition system, based on artificial neural networks. Synthesis with 65 nm CMOS std _cells returns a power dissipation below 2 μ W and an area of about 0.05 mm 2 , Results are the current state-of-the-art for this kind of system and they are very promising for the future integration in smart sensors for wearable applications.
In this paper, for the first time in the literature, a custom circuit is proposed to process the heavy calculations needed to change in real-time the reference coordinate system of vectors measured by tri-axial accelerometers, in order to make a pre-processing stage for the building of virtual sensors like linear and gravity accelerometers. To this purpose, a new "hardware friendly" algorithm has been derived which can be implemented in a more compact iterative structure to combine high accuracy and low power consumption, in order to conveniently integrate it into the circuitry of smart accelerometers. Synthesis with 65 nm CMOS std_cells returns a power dissipation of 0.89 μW and an area of about 0.024 mm 2 . Results are the current state-of-the-art for this kind of applications and they are very promising for the future integration in smart sensors for wearable applications.
Abstract Treatment of patients with chronic stable angina has two main objectives: to improve clinical outcome and to reduce angina symptoms. Prognosis is mainly improved by a reduction in cardiovascular risk factor burden, which may be achieved by appropriate lifestyle changes and, for some risk factors (e.g. hypercholesterolaemia, hypertension, diabetes), appropriate pharmacological therapy (including, in particular, statins and renin–angiotensin–aldosterone system inhibitors) and use of antithrombotic agents. Symptoms can be improved by a variable combination of traditional (beta-blockers, calcium channel blockers, nitrates) and novel (e.g. ivabradine, ranolazine) anti-ischaemic drugs, which may act through reduction in myocardial oxygen consumption and/or improvement of myocardial perfusion.
Abstract Background Left main coronary artery disease (LMCAD) heavily affects prognosis of patients with suspected CAD. Thus, its identification/exclusion is an important step in the assessment of these patients. Although being the gold standard to identify LMCAD, invasive coronary angiography (ICA) is burdened by some risks, while coronary computed tomography angiography (CCTA) has still limited availability, quite high costs and associated radiologic risks. In the past decades, several studies demonstrated the utility of ECG exercise stress test (EST) for the identification of LM disease in patients with suspected CAD. However, the pre-test probability of CAD of subjects undergoing EST has significantly changed in the last decades. Accordingly, in this study we aimed to assess the predictive value of EST for the presence/absence of LMCAD in a contemporary population of patients with suspected CAD. Methods We retrospectively enrolled 495 consecutive patients, referred to our Center between years 2018 and 2021 because of suspected CAD, who underwent both an EST (standard treadmill Bruce protocol) and ICA (within 12 months of the EST). Patients with a history of coronary artery bypass surgery were excluded. Results Overall, 24 patients (4.8%) were found to have LMCAD at ICA. Among clinical variables, only male gender (p=0.025) and smoking (p=0.003) were associated with LMCAD. A number of ECG leads with EST-induced ST-segment depression (STD) ≥5 and a maximal STD ≥2 mm were more frequently found in patients with, compared to those without LMCAD (29.2 vs 9.8%, p=0.003; and 58.3 vs 24.8%, p<0.001, respectively). No other EST variable was associated with LMCAD, including ST-segment elevation in lead aVR (4.2 vs. 2.6% in the 2 groups, respectively, p=0.63). On the other hand, among the 206 patients (41.6% of the population) who achieved 85% of maximal heart rate predicted for age and had ST-segment depression < 2mm, LMCAD was present in 1.9% only. Conclusions Our data indicate that EST continues to be a valuable tool for predicting the presence/absence of LMCAD in contemporary populations of patients with suspected coronary artery disease.
Human Activity Recognition requires very high accuracy to be effectively employed into practical applications, ranging from elderly care to microsurgical devices. The highest accuracies are achieved by Deep Learning models, but these are not easily deployable in handheld or wearable devices with very constrained resources. We therefore present a new HAR system suitable for a compact FPGA implementation. A new Binarized Neural Network (BNN) architecture achieves the classification based on data from a single tri-axial accelerometer. From our experiments, the effect of gravity and the unknown orientation of the sensor cause a degradation of the accuracy. In order to compensate for these issues, we propose a HW-friendly algorithm to pre-process the raw acceleration signal. Moreover, the very low power and hardware friendly BNN has been trained and validated on the PAMAP2 dataset, for which the pre-processing operations increase the accuracy from 51% to 99% in the best case. Aiming for a low-power design, we designed both a custom circuit to perform the pre-processing operations and a hardware accelerator for the BNN. The design on FPGA features a power dissipation of 72 mW and occupies 6788 LUTs.
