Highly crystalline and transparent CdS films are grown by utilizing the vacuum thermal evaporation (VTE) method. The structural, surface morphological, and optical properties of the films are studied and compared with those prepared by chemical bath deposition (CBD). It is found that the films deposited at a high substrate temperature (200 °C) have a preferential orientation along (002) which is consistent with CBD-grown films. Absorption spectra reveal that the films are highly transparent and the optical band gap values are found to be in a range of 2.44 eV–2.56 eV. CuIn1−xGaxSe2 (CIGS) solar cells with in-situ VTE-grown CdS films exhibit higher values of Voc together with smaller values of Jsc than those from CBD. Eventually the conversion efficiency and fill factor become slightly better than those from the CBD method. Our work suggests that the in-situ thermal evaporation method can be a competitive alternative to the CBD method, particularly in the physical- and vacuum-based CIGS technology.
Silicon on insulator (SOI)-based transistors gated by nanogranular SiO2 proton conducting electrolytes were fabricated to mimic synapse behaviors. This SOI-based device has both top proton gate and bottom buried oxide gate. Electrical transfer properties of top proton gate show hysteresis curves different from those of bottom gate, and therefore, excitatory post-synaptic current and paired pulse facilitation (PPF) behavior of biological synapses are mimicked. Moreover, we noticed that PPF index can be effectively tuned by the spike interval applied on the top proton gate. Synaptic behaviors and functions, like short-term memory, and its properties are also experimentally demonstrated in our device. Such SOI-based electronic synapses are promising for building neuromorphic systems.
2D materials with atomically thin nature are promising to develop scaled transistors and enable the extreme miniaturization of electronic components. However, batch manufacturing of top-gate 2D transistors remains a challenge since gate dielectrics or gate electrodes transferred from 2D material easily peel away as gate pitch decreases to the nanometer scale during lift-off processes. In this study, an oxidation-assisted etching technique is developed for batch manufacturing of nanopatterned high-κ/metal gate (HKMG) stacks on 2D materials. This strategy produces nano-pitch self-oxidized Al
Abstract Two-dimensional (2D) structures composed of atomically thin materials with high carrier mobility have been studied as candidates for future transistors 1–4 . However, owing to the unavailability of suitable high-quality dielectrics, 2D field-effect transistors (FETs) cannot attain the full theoretical potential and advantages despite their superior physical and electrical properties 3,5,6 . Here we demonstrate the fabrication of atomically thin single-crystalline Al 2 O 3 (c-Al 2 O 3 ) as a high-quality top-gate dielectric in 2D FETs. By using intercalative oxidation techniques, a stable, stoichiometric and atomically thin c-Al 2 O 3 layer with a thickness of 1.25 nm is formed on the single-crystalline Al surface at room temperature. Owing to the favourable crystalline structure and well-defined interfaces, the gate leakage current, interface state density and dielectric strength of c-Al 2 O 3 meet the International Roadmap for Devices and Systems requirements 3,5,7 . Through a one-step transfer process consisting of the source, drain, dielectric materials and gate, we achieve top-gate MoS 2 FETs characterized by a steep subthreshold swing of 61 mV dec −1 , high on/off current ratio of 10 8 and very small hysteresis of 10 mV. This technique and material demonstrate the possibility of producing high-quality single-crystalline oxides suitable for integration into fully scalable advanced 2D FETs, including negative capacitance transistors and spin transistors.
Graphene is a promising candidate for the thermal management of downscaled microelectronic devices owing to its exceptional electrical and thermal properties. Nevertheless, a comprehensive understanding of the intricate electrical and thermal interconversions at a nanoscale, particularly in field-effect transistors with prevalent gate operations, remains elusive. In this study, nanothermometric imaging is used to examine a current-carrying monolayer graphene channel sandwiched between hexagonal boron nitride dielectrics. It is revealed for the first time that beyond the expected Joule heating, the thermoelectric Peltier effect actively plays a significant role in generating hotspots beneath the gated region. With gate-controlled charge redistribution and a shift in the Dirac point position, an unprecedented systematic evolution of thermoelectric hotspots, underscoring their remarkable tenability is demonstrated. This study reveals the field-effect Peltier contribution in a single graphene-material channel of transistors, offering valuable insights into field-effect thermoelectrics and future on-chip energy management.
Silicon nanomembrane (SiNM) transistors gated by chitosan membrane were fabricated on plastic substrate to mimic synapse behaviors. The device has both a bottom proton gate (BG) and multiple side gates (SG). Electrical transfer properties of BG show hysteresis curves different from those of typical SiO 2 gate dielectric. Synaptic behaviors and functions by linear accumulation and release of protons have been mimicked on this device:excitatory post-synaptic current (EPSC) and paired pulse facilitation behavior of biological synapses were mimicked and the paired-pulse facilitation index could be effectively tuned by the spike interval applied on the BG. Synaptic behaviors and functions, including short-term memory and long-term memory, were also experimentally demonstrated in BG mode. Meanwhile, spiking logic operation and logic modulation were realized in SG mode.
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