Ajoy Mandal

Texas Instruments (India)

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Co-Authors

Sudeb Dasgupta

Indian Institute of Technology Roorkee

Ramakrishnan Venkatraman

Arizona State University

Anand Bulusu

Indian Institute of Technology Roorkee

Lomash Chandra Acharya

Indian Institute of Technology Roorkee

Arvind K. Sharma

IMEC

Mahipal Dargupally

Indian Institute of Technology Roorkee

Khoirom Johnson Singh

Indian Institute of Technology Roorkee

Neeraj Mishra

Indian Space Research Organisation

Nayakanti Sai Shabarish

Intel (India)

Neha Gupta

Indian Institute of Technology Roorkee

Cooperative Institutions

Indian Institute of Technology Roorkee

Texas Instruments (United States)

Texas Instruments (India)

IMEC

All India Institute of Hygiene and Public Health

Sardar Vallabhbhai National Institute of Technology Surat

National Institute of Technology Srinagar

KPC Medical College and Hospital

University of Sydney

University of Washington

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Switching Activity Factor-Based ECSM Characterization (SAFE): A Novel Technique for Aging-Aware Static Timing Analysis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2024)

Lomash Chandra Acharya Arvind K. Sharma Neeraj Mishra Khoirom Johnson Singh Mahipal Dargupally

Characterization

Factor (programming language)

10.1109/tcad.2024.3396432

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Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure

Lomash Chandra Acharya Anubhav Kumar Khoirom Johnson Singh Neha Gupta Nayakanti Sai Shabarish

This article proposes a method for performing device-level variability-aware static timing analysis (STA) on digital circuits using a tool flow methodology based on Python and Bash scripting. The method involves creating an effective current source model (ECSM) .libs file with a custom tool flow, which incorporates variation-aware timing models of standard cells to minimize recharacterization efforts. The resulting file is integrated into an industry-standard STA tool environment to assess the impact of device and layout level variability on digital timing closure. The simulation work is carried out using Mentor Graphics ELDO SPICE, Synopsys DC Compiler, and PrimeTime STA environment in STMicroelectronics (STM) 65 nm CMOS process. This tool flow reduces recharacterization efforts by 98.13% compared to conventional SPICE simulation by incorporating the impact of device-level variability on the conventional STA flow.

Spice

Python

10.1109/smacd58065.2023.10192158

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Citations (2)

Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2022)

Lomash Chandra Acharya Arvind K. Sharma Neeraj Mishra Khoirom Johnson Singh Mahipal Dargupally

A static timing analysis (STA) methodology based on an effective current source model (ECSM) is proposed for the first time for estimating the aging-aware path-level timing performance and its impact on the logical effort of a CMOS inverter for digital timing closure in pre-stress and post-stress conditions. Degradation in the threshold voltage

$(V_{\mathrm{ th}})$

of PMOS occurs due to temporal variability mechanisms (aging), such as negative bias temperature instability, resulting in delay degradation of a standard cell. Therefore, we proposed a technique to make the STA process aware of this degradation by developing device-level variation aware (with aging) timing models of CMOS inverters to represent threshold-crossing points (TCPs) in an ECSM.libs file as a function of stress time (

$t$

). A device-level approach for

$V_{\mathrm{ th}}$

degradation into different aging conditions, such as static and dynamic, is developed for a given process design kit to update TCPs in a (.libs) file as a function of

$t$

. A python-based tool is being developed to estimate the path-level timing performance of digital circuits in pre- and post-stress conditions. Again, we developed a technique for relating the inverter’s logical effort with

$t$

to resize a near-critical path in pre-stress conditions for achieving digital timing closure in pre- and post-stress conditions. The verification and validation of the proposed model with different benchmark circuits are performed using a parasitic extracted netlist in the Eldo SPICE environment with the 65-nm CMOS process technology. Finally, our model reduces the number of SPICE/Stress simulations by 98.13% compared to the previously reported only simulation-based techniques.

10.1109/tcad.2022.3231173

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Citations (4)

Health, Equity and Poverty Exploring the Links in West Bengal, India

Barun Kanjilal Moumita Mukherjee Shabda Singh Swadhin Mondal D. Barman

BENGAL

Equity

West bengal

Source

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Citations (9)

Prediction of variation aware F in ring oscillators (ROs) to mitigate the impact of aging on RO-PUF

Solid-State Electronics (2023)

Lomash Chandra Acharya Khoirom Johnson Singh Neha Gupta Mahipal Dargupally Neeraj Mishra

Spice

Ring oscillator

Cadence

10.1016/j.sse.2023.108790

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DFM: Impact analysis in a high performance design

S M Stalin Amit Brahme Ramakrishnan Venkatraman Ajoy Mandal

Layout context effects play a significant role in determining circuit performance in advanced technology nodes. In this paper, a study of the common design practices to tackle the increasing process variations in advanced CMOS technologies is also done. We highlight a method by which we have tackled the challenge of modeling these effects in the critical paths of a large System-on-Chip (SoC) design. We describe an approach to handle these variations when analyzing clock trees and data paths for design timing. The methodology models the true cell context in design layout to comprehend the impact of context specific process variations.

Integrated circuit design

Static timing analysis

Integrated circuit layout

Design process

Standard cell

Process design

10.1109/isqed.2011.5770712

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Citations (1)

Variation Aware Timing Model of CMOS Inverter for an Efficient ECSM Characterization

Lomash Chandra Acharya Arvind K. Sharma Venkatraman Ramakrishan Ajoy Mandal Sudeb Dasgupta

In static timing analysis (STA), delay estimation of CMOS standard cells is accomplished by the effective current source model (ECSM) characterization method. ECSM characterization stores the values of threshold crossing points (TCP's) of output voltage in a look-up table for the combination of input transition time (T _R ) and load capacitance (C _L ). Due to variability, re-characterization of entire cell library is required to update the look-up tables of TCP's, which is a tedious task. Due to temporal variability mechanisms such as negative bias temperature instability (NBTI) and hot carrier injection (HCI), non-critical paths may become critical. Therefore, a large coverage of TRs in characterization is required. In this work, an analytical timing model for delay estimation of CMOS inverter with large TR coverage is proposed. This model matches well with HSPICE simulation with a maximum error of 3%. With this timing model, the ECSM characterization of CMOS inverter can be accomplished with very few HSPICE simulations compared to traditional approaches. The model coefficients are correlated with device/layout level parameters such as driving strength (W) or number of layout fingers (NF), supply voltage (V _dd ), threshold voltage (V _th ), and mobility (u). Furthermore, with this model, re-characterization efforts can be reduced significantly in comparison to conventional approach and variability analysis could be done without exercising Monte-Carlo analysis.

Standard cell

Characterization

10.1109/isqed51717.2021.9424341

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Citations (8)

Optimal Choice of Waveform for Library Characterization for Accurate Delay Calculation

Ajoy Mandal Saili Shete

Accuracy of waveform aware delay calculation approaches in STA tools require selection of an appropriate driver waveform during library characterization. The optimal waveform shape is dependent on process corner, voltage, temperature, parasitics and also the properties of the transistors involved. Traditionally used ramp waveform is not suitable for accuracy particularly at lower voltages and temperatures. Identification of waveform shape across a wide range of operating corners and for different transistor types can involve significant cost in terms of resources and time. This paper discusses an efficient approach for finding the driver waveform for library characterization. It also enlists the factors that influence the waveform shape and the related careabouts during the waveform identification process. Lastly, it proposes an approach to reduce the run-time and resources used to get the optimal characterization waveform at all operating corners.

Identification

Parasitic extraction

10.1109/isqed48828.2020.9137033

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Optimization strategies to improve statistical timing

P.A. Viswanath Pranav Murthy D.V. Das R. Venkatraman Ajoy Mandal

Statistical static timing analysis (SSTA) has been used in practice as an extension to regular static timing analysis (STA) to analyse for the impact of process variations on timing in new process nodes. However, the use of statistical timing in design optimization is a challenge that chip design teams face. In this paper, we propose some approaches to enable the comprehension of statistical timing behaviour during optimization. We indicate how the design standard-cell library can be analysed for variation, to help in understanding the robustness of cells, and in enabling the use of the correct logic architectures. We then propose an approach to comprehend the statistical timing behaviour in conventional (static-timing-based) optimization engines. We show how this method helps in optimising the overall area of the design, while simultaneously improving the timing characteristics. We also indicate a complementary approach of incrementally optimising the design using the statistical characteristics of the library as an added cost for sizing. We show how these approaches resulted in a 9.1% reduction in design area, and a direct improvement in statistical timing of a complex real-life design.

Static timing analysis

Robustness

Process Variation

Variation (astronomy)

Integrated circuit design

Statistical Analysis

10.1109/isqed.2009.4810341

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Citations (2)

Enhancing Design Robustness Accounting for Process Variations of Multi-transistor Designs

Ajoy Mandal

Semiconductor device performance is impacted by variations in the manufacturing process. Modeling of such variations in the design process and accounting for their impact on chip timing and electrical specs is key to ensuring high yielding parts post manufacturing. Circuits created with multiple transistor types require to comprehend the interdependencies between variations of different transistors. In this paper we discuss about challenges related to handling of such variations in design closure process of integrated circuits involving multiple transistor types.

Robustness

Semiconductor device fabrication

Integrated circuit design

Transistor model

Process Variation

10.1109/edtm58488.2024.10512316

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