We develop a simple experimental approach to remove bulk trap contributions from charge pumping data collected on devices which suffer from large amounts of bulk dielectric electron trapping. The approach is more desirable and easier to implement than other simulation/device modeling based approaches. We demonstrate the approach using HfO 2 based MOSFETs. Additionally, we provide an explanation for the smaller than expected bulk trap contribution to charge pumping current.
Under a given stress field, the recoverable component (R) for HfO 2 p-MOSFET appears almost constant at lower temperatures but shows a progressive decrease at higher temperatures. Similar conclusion can also be obtained for HfSiON p-MOSFET. Evidence shows that the decrease in R is due to its transformation into a more permanent form (P). We show that those switching hole traps (SHTs) responsible for the R share the same origin as a portion of bulk traps responsible for the stress induced leakage current (SILC) and 1/f noise of the high-k gate p-MOSFET. When the density of SHTs is constant, no increase in 1/f noise and SILC, i.e. no apparent generation of bulk traps, is observed after NBTI stress. An increase in the SILC and 1/f noise, which implies the generation of bulk traps, is observed when part of these SHTs are transformed into relatively permanent bulk traps, allowing them to be sensed by the slow SILC and 1/f noise measurements.
For the first time, we provide mechanistic understanding of high gate leakage current on surface channel SiGe pFET with high-k/metal gate to enable sub 1nm EOT. The primary mechanism limiting EOT scaling is Ge enhanced Si oxidation resulting in a thick (1.4nm) SiO x interface layer. A secondary mechanism, Ge doping (≥4%) in high-k, possibly by up diffusion, also results in higher leakage. With this understanding, we optimized high-k nitridation reducing O and Ge diffusion to achieve EOT=0.91nm directly on SiGe with leakage equivalent to bulk Si. High I on (1.5× Si), and low subthreshold slope (73mV/dec) are also achieved. This mechanism enables high mobility channel gate dielectric development directly on SiGe without the need for Si cap, simplifying processing and device design.
The effects of high-pressure annealing on interface properties and charge trapping of nMOSFET with high-/spl kappa/ dielectric were investigated. Comparing with conventional forming gas (H/sub 2//Ar=4%/96%) annealed sample, nMOSFET sample annealed in high-pressure (5-20 atm), pure H/sub 2/ ambient at 400/spl deg/C shows 10%-15% improvements in linear drain current (I/sub d/) and maximum transconductance (g/sub m,max/). Interface trap density and charge trapping properties were characterized with charge pumping measurements and "single pulsed" I/sub d/-V/sub g/ measurements where reduced interface state density and improved charge trapping characteristics were observed after high pressure annealing. These results indicate that high pressure pure hydrogen annealing can be a crucial process for future high-/spl kappa/ gate dielectric applications.
Currently, transition metal dichalcogenides (TMDs) are under intense investigation due to their potential uses. [1] One reason for the interest is because TMDs exhibit a bandgap. This provides a key aspect that can enable their use in future transistors as alternative channel materials with high mobility values while also providing robust on/off ratios. Because of the need to overcome the short channel effects and lower the power consumption of field effect transistors (FETs) as their dimensions scaled down drastically, extensive research has been done on layer-by-layer TMDs over the past few years. [2-4] Furthermore, due to the variety of TMDs, which results in different bandgaps and overall offsets [5], there are theoretical predictions suggesting that TMDs are best introduced in “broken gap” tunneling field effect transistors (TFETs). Some of these device designs include dielectrics in contact with TMD material. As we wait for advances in TMD materials growth, researchers are investigating relevant TMDs with most transistor structures being bottom gate devices for the ease of integration with an emphasis on the TMD material. However, there have been very few studies to investigate high-k dielectrics on these TMD materials. [6-8] Furthermore, even fewer studies are done on the interface characterization between dielectric and TMD, with even fewer still on the evaluation of this interface electrically [9, 10] and the implications to device performance and reliability. An obstacle of integrating high-k dielectrics on these two-dimensional (2-D) materials is the lack of bonds available at the surface that enables thin film deposition. On the other hand, the research on metal/TMD contacts is also important to improve the transistor performance. To reduce the contact resistance, the metal selection [2], doping techniques [11] and the understanding of carrier transport near the metal/TMD interface [12] still require scientific investigation. Therefore, in this work, we will demonstrate top-gated few-layer MoS 2 transistors with HfO 2 dielectric and the subsequent electrical characterization. Few-layer MoS 2 flakes were exfoliated from commercial natural MoS 2 crystals and transferred onto the SiO 2 /Si substrate. Using photolithography with a lift-off process, the source and drain of the transistor were formed with Au / Ti. Thereafter, a 15-minutes in-situ UV-O 3 surface functionalization [6] was performed, and HfO 2 was deposited at 200˚C using atomic layer deposition (ALD) immediately after the treatment. The final step of fabrication was deposition and patterning of Au / Cr metal gate. Electrical measurements were performed using a Keithley 4200 SCS and an Agilent E4980A LCR meter. The interface between MoS 2 and HfO 2 was studied by capacitance-voltage (C-V) measurements. Interface trap density (D it ) was extracted using the conventional high-low frequency method. From the characterization results of a MoS 2 transistor, the I DS -V GS exhibited an I on /I off ratio of 10 6 , and an ultra-low leakage current (~10 -14 A) indicating a continuous dielectric thin film. In C-V measurements, a “hump” was observed in the depletion region, which indicates a large number of interface traps in the gate stack. It explains the SS degradation in the I-V measurements. The I DS -V DS curves show a non-linear region at low V DS, which are caused by non-optimized contacts. Moreover, we extracted the D it , where a peak value of 1.2×10 13 cm -2 eV -1 was extracted. More physical characterization and analysis are needed to understand the origin of these interface traps. With this transistor test structure; however, the ability to study other TMDs beyond MoS 2 , HfO 2 , and Au/Ti contacts are possible. This work is partially funded by National Science Foundation (NSF) award 1407765. References: [1] Q. H. Wang, et al., Nat. Nano. , 7 , p. 699, 2012. [2] S. Das, et al., Nano Letters , 13 , p. 100, 2012. [3] H. Liu et al., IEEE EDL , 33 , p. 546, 2012. [4] B. Radisavljevic, et al., Nat Nano , 6 , p. 147, 2011. [5] C. Gong, et al., APL , 103 , p. 053513, 2013. [6] A. Azcatl, et al., APL, 104 , p. 111601, 2014. [7] S. McDonnell, et al., ACS Nano, 7 , p. 10354, 2013. [8] J. Yang, et al., ACS Appl. Mat. & Int., 5 , p. 4739, 2013. [9] W. Zhu, et al., Nat. Comm. , 5 , p. 3087, 2014. [10] P. Zhao, et al., Microelectron. Eng. , 147 , p. 151, 2015. [11] H. Fang, et al., Nano Lett. , 13 , p. 1991, 2013. [12] H. Liu, et al., ACS Nano , 8 , p. 1031, 2014. Figure 1
In this work, thin epitaxial layers of dielectric barium titanate (BaTiO3 or BTO) were grown on Nb-doped strontium titanate (001) substrates using either molecular beam epitaxy or atomic layer deposition and then electrically stressed to the point of breakdown. The BTO layer thicknesses were in the range of 20–60 nm, and typical breakdown fields were in the range of 1.5–3.0 MV/cm. Electron microscopy and electron energy-loss spectroscopy (EELS) were used to provide information about the degradation mechanism. High-resolution imaging revealed widespread structural damage in the BTO films after breakdown had occurred, with substantial polycrystallinity as well as amorphous regions. EELS analysis of the stressed films showed characteristic signatures of valence change in the Ti L23 EELS spectra associated with the accumulation of oxygen vacancies. Stressed heterostructures that had been patterned by electron lithography showed similar trends, including degraded crystallinity as well as oxygen loss.
In this work, we report high performance (I on ~1 mA/μm at Ioff 100nA/μm @ 1V Vcc) short channel p-type SiGe/Si FinFETs combining high mobility, low T inv (scaled High-k w/o Si cap), low R sd , and process-induced strain. A dual channel scheme for high mobility CMOS FinFETs is demonstrated.
A mechanism of degradation and breakdown in high-k/metal gate transistors was investigated. Based on the electrical test, physical analysis, and modeling results, we propose that the breakdown path formation/evolution in the interfacial SiO 2 layer is associated with the growth of an oxygen-deficient filament facilitated by the grain boundaries of the overlaying high-k film. The model allows reproducing SILC temperature dependency and its exponential increase from the fresh through soft and progressive breakdown phases.
Accurate reliability predictions of real-world digital logic circuits rely heavily on the relevancy of device-level testing. In the case of bias temperature instability (BTI), where recovery plays a significant role, a leap of faith is taken to translate device-level reliability data into a practical information for the real-world circuit implications. In this paper, we develop a methodology to bridge this gap by employing an eye diagram approach, which allows us to monitor, at circuit speed, device-level random jitter degradation in response to stress. By employing a variety of positive BTI gate voltage stress and sense bit sequences (including dc, ring oscillator (RO), and pseudorandom), we are able to compare the effectiveness of these approaches at capturing random timing jitter. We find that conventional RO-type measurements are unable to capture the random jitter degradation. This calls into question the effectiveness of using RO structures as a proxy for real-random logic circuits. Only when a pseudorandom bit sequence is employed does the true extent of jitter degradation become observable. This is an important development and serves as an accurate means to translate device-level reliability data to predict real-world digital logic circuit degradation.
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