To satisfy the ever-increasing demand for higher density (functionality) and lower power (portability), the dimensions and operating voltages of the modern electronic devices are being reduced frequently. This has brought new challenges both from the technology and materials point of view. One such issue is soft error, the temporary malfunction of device caused by the effect of radiation on the Si ICs. One such radiation is high energy alpha particle whose main source is the solders used in the packaging. The continued scaling of complementary metal oxide semiconductor device technologies has led to continued device shrinkage and decreases in the operating voltage of the device transistors. Scaling has meant denser circuitry overall, thinner silicon (e.g., silicon on insulator) in logic applications, and less charge on capacitors for volatile memory. These trends have resulted in devices being more sensitive to soft errors since now low energy alpha particles can flip a memory bit or alter timing in a logic circuit. Due to the use of flip-chip joints and developments towards 3D packaging, the solder bumps have moved very closer to the active Si devices, where even the low energy alpha ray having short range is able to induce soft error. One of the major sources of alpha particle radiation is the solders used for joining components in the packaging and they contain alpha emitters and there is increasing demand of Low Alpha activity Pb-free solders. The present paper reviews the issue of soft error in depth covering its historical background, causes and effects on electronic devices along with mitigation efforts. The importance of low alpha solders in microelectronics packaging applications is discussed in the light of soft-error issue.
Chip stacking with through-silicon-vias (TSV) technology for 3-D packaging of electronic devices was investigated. A new process of direct solder bumping on Si wafers without photoresist (PR) mould was designed and applied in this study. The Cu extrusion process on the via was also omitted for process simplification. This simplified process can be useful for cost reduction and increased productivity. The substrate for the experiments was a p-type 〈100 〉 Si wafer of 100 mm diameter. In order to produce the vias, the Si wafer was etched by a deep reactive ion etcher (DRIE) using SF 6 and C 4 F 8 plasmas alternately. The produced vias were 40 μm in diameter and 80 μm in depth. On the via side walls, SiO 2 , Ti, and Au layers were formed with thicknesses of 1, 0.1, and 0.7μm, respectively. Pulsed direct current (DC) electroplating was used to fill the vias with Cu. Then the Si wafer was back ground to a thickness of 80 μm until the Cu filling in the vias was exposed to the surface without extrusion. Plating current subsequently flowed through the vias to the bumping surface, and Sn was electroplated on the Cu filling directly without a PR mould. To optimize the bumping process, the current density and time for Sn plating were varied from 0.04 to 0.06 A/cm 2 and from 10 to 40 min, respectively. Bumps with a height of 20 μm were formed successfully with 0.05 A/cm 2 and 30 min without a PR mould. The bump height increased with increasing plating current and time; for example, from 13 μm at 10 min to 33 μm at 40 min in case of 0.06 A/cm 2 . The Si dice with electroplated Sn bumps had dimensions of 5 × 5 mm and thickness of 80 μm. Three Si dice were stacked successfully by micro-soldering at 260°C. In the interface between the Sn bumps and the Cu filling, a Cu 6 Sn 5 intermetallic compound was produced with a thickness of 3.2 μm. Through this study, a process for non-PR solder bumping by electroplating and wafer stacking with TSV was achieved successfully.
Recently, the electronics industry is developing toward artificial intelligence, the Internet of things, fifth-generation technology, and high-performance computing. High-density electronics packaging, high speed, high performance, and miniaturized size are required to satisfy these trends. Three-dimensional Si-chip stacking using through-Si via (TSV) has attracted the attention of industries related to these requirements. In this study, TSV fabrication using the deep reactive ion-etching process and the coating of functional layers on the TSV wall, such as insulating, adhesion, and seed layers, were investigated. In addition, Cu electroplating in the TSV was analyzed in detail. The solutions to other accompanied technical barriers for packaging high-density electronics can improve smartness and con- venience. Key words: Three dimensional packaging, Through-Si-Via, Functional layers, Electroplating
Sn-based lead-free solders such as Sn-Ag-Cu, Sn-Cu, and Sn-Bi have been used extensively for a long time in the electronic packaging field. Recently, low-temperature Sn-Bi solder alloys attract much attention from industries for flexible printed circuit board (FPCB) applications. Low melting temperatures of Sn-Bi solders avoid warpage wherein printed circuit board and electronic parts deform or deviate from the initial state due to their thermal mismatch during soldering. However, the addition of alloying elements and nanoparticles Sn-Bi solders improves the melting temperature, wettability, microstructure, and mechanical properties. Improving the brittleness of the eutectic Sn-58wt%Bi solder alloy by grain refinement of the Bi-phase becomes a hot topic. In this paper, literature studies about melting temperature, microstructure, inter-metallic thickness, and mechanical properties of Sn-Bi solder alloys upon alloying and nanoparticle addition are reviewed.
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